SU131777A1 - Shift Register - Decoder - Google Patents

Description

Magnetic core decoder circuits with a rectangular hysteresis loop and semiconductor triodes (matrix interpretation) are known, which contain a receiving cumulative shift register. The disadvantage of these decoder circuits, which require n9 magnetic cores and the same number of amplifying triodes (is the number of binary bits of the code being decoded), is their multi-elementity and the need to have an additional device at the input for obtaining a return code that fills the zeros in the forward code.

The proposed decoder circuit differs from the known ones in that, in order to reduce the number of circuit elements, decipherment is carried out in the very receiving storage shift register, built on magnetic cores with a rectangular hysteresis loop. To this end, on each of the shift register torques, the main windings (input, output, and clock), there are deciphering windings to which semi conductor triodes are connected, the bases of which are connected in series with the interpreter windings and sensor windings of units. The principle of decoding is based on the comparison of the voltage induced in the decoding windings at the time of the switching of the tori with clock pulses with the reference voltage received from the sensor units (the latter acts as a device for receiving the reverse code). The number of decryption windings is determined by the number of decimal outputs.

A schematic diagram of the proposed cumulative shift register-decoder for three bits is shown in the drawing. The shift register is made using a single-ended scheme with a controlled bit chain.

Suppose that input 1 of the register arrives and information with the code OH. Then, when the first pulse of the given code arrives (the code pulses follow between clock pulses), the torus 2 switches

№131777-2B state "1. When a clock pulse arrives, the passage and its along a chain of series-connected windings 3, this torus switches to the state "o"; a voltage of such polarity arises in its output winding 4 that, passing through the diode 5 of the delay circuit 6, it charges the capacitor 7. The capacitor discharge circuit at this point in time is broken by the key circuit 8. At the end of the clock pulse, the key circuit is closed and the capacitor 7 is discharged to the input winding 5 of the next torus 10. Thus, under the action of the clock pulse, the information rushed one step. Consequently, when the second clock pulse arrives in state "1", tori 10 and 11 will be switched.

When the third clock pulse arrives from the signal coming from the distributor for 12 cycles, built on magnetic cores and controlled from the same clock source, triode 13 will open. At the same time, the voltage generated on the decoding windings connected in series will be compared. 14 of the cumulative shift register with the voltage appearing on the reference torus 5. From the circuit it is obvious that for the chosen example (information with code 011) the output control voltage (negative polarity is only on the upper row of decoupling windings (at the input of triode 16), while on the other row of windings there will be a resultant voltage of positive polarity to which the amplifying triode 17 does not react.

Diodes 18 and 19 serve to prevent the amplification triodes 16 and 17 from opening in the balancing currents at the moment they move through the shift register information received at the input of the decoder. The capacitors 20 and 21 are designed to block the inputs of the amplifier stages from impulse noise arising at the time of decoding due to an inaccurate coincidence in the duration of the pulses generated in the deflecting windings and the windings of the supporting torus. In addition, these noise pulses in the amplifier stages are limited by the positive automatic mixing applied to the triode bases from the voltage divider composed of resistances 22 and 23. Setting up the circuit reduces to selecting the voltage on the windings of the supporting torus by changing the submagical current by resistance 24 and variations in the voltage of the automatic bias on the amplifier stages by the resistance 22.

Subject invention

A shear-decoder on magnetic cores with a right-angle hysteresis loop and semiconductor triodes, characterized in that, in order to reduce the number of circuit elements, decrypt windings are located on each of the magnetic cores, the number of which is equal to the number of outputs of the decoder to which the semiconductor triodes are connected, The bases of which are connected in series with the decrypting windings and sensor windings of "units, which serve to sum the induced voltages when the code is deciphered.