SU370731A1 - COUNTER OF PULSES IN GREY CODE - Google Patents

Description

one

Izab (retirement to the field of discrete automation and computing.

A pulse counter in the Gre code is known, containing triggers of the main and additional bits made on the memory elements with non-destructive readout, for example, two transfluxors with windings, diode valves and l-blocks qpax.

The aim of the invention is to reduce the power of zag / jump and read pulses.

For this, one of the output windings of each transfluxor is connected to a series-connected diode and parallel-connected capacitors and the RESISTANT: 1. The connection points of capacitors and resistors with the output windings of both transfluxors of each trigger are interconnected and form the transfer inputs of these triggers, and the points of connection of the capacitors, resistors and the transfluxor diodes of each trigger form, respectively, the left and right outputs of the triggering triggers, which in 1 each 5 ii3 triggers of all the main discharge a counter nachi first, sootvetstveimo connected to the counting input and output transfer trigger and subsequent discharge. In the additional discharge trigger, the specified inputs are connected respectively to the transfer input and the counting input of the first main discharge trigger, the transfer input of the additional discharge trigger is connected to the counting input of this trigger and connected to the trigger pulse bus. The windings of reading and setting the triggers of all bits into the "zero state" are connected in series and connected to the corresponding inputs of the counter.

The drawing shows a circuit diagram of the proposed device.

The device contains triggers of main 1 and 2 and additional 3 bits, performed, for example, on transfluxors 4 and 5 with windings 6-11, dyuyud 12-17, capacitors

18-21 and resistors 22, 23. inputs 24-26 and outputs 27-32.

The alternating signal from the reading generator is fed from input 25 continuously through the connected windings 9 in series

Read all transfluxors. From the output windings 10 and // unlocked transfluxor - / (5) of each trigger, the alternating current enters through diodes 14 (15) and 13 (16) to charge the storage capacitor

and the driving capacitor 18 (21) of this trglfluxor. The charge time of these capacitors with selected circuit circuits is determined by the power of the read pulses and their frequency. Since the frequency

read pulses choose more

frequency of triggering pulses, the power of the reading generator may be small.

The energy accumulated on the capacitors 19 (20) is used to switch the trigger on the counting input and output a signal to external circuits. The switching of the trigger in the counting mode is ensured by closing the discharge circuits of the capacitors 19 and 20 through the windings 7 and 5 of the transfluxors 4 and 5 and an external switch connected to the counting input of the trigger and controlled by the source of the immersions.

The serially connected windings 7 and 5 are connected to capacitors 19 and 20 in such a way that the discharge current of capacitor 19 sets the transfluxor 5 to the state "1 and the transfluxor 4 to the state" O, and the discharge current of the lcdqpa 20 is vice versa (transfluxors 4 and 5 are set respectively to state "1 and" O).

Diodes 14 and 15 are valves in the charge circuit of capacitors 19 and 20, diodes 13 and 16 are in the circuit of capacitors 18 and 21, and diodes 12 and 17 separate the discharge circuit of capacitors 19 and 20.

When the triggering input 26 enters, unconditional switching of trigger 3 of the additional discharge of the counter takes place as a result of discharge of the capacitor 19 (20) of this trigger through windings 7 and 8 of transfluxor 4 and 5 and external key (input 26).

The trigger / first (main) bit is switched at the moment the triggering pulse arrives at input 26 under the condition that the two capacitors 21 of the trigger 3 are not charged, i.e. the zero state of this trigger. In this case, the capacitor 19 (20) of the first discharge trigger is discharged through the windings 7 and 5 of the transfluxors of this trigger, which triggers the triple capacitor 21 of the preload discharge and the external switch (input 26).

When a charged additional capacitor 21 is triggered, i.e. when this trigger is in the state "1", the first-stage storage capacitor of the trigger does not discharge due to the counter-switched voltages of these capacitors, and the first discharge trigger does not switch.

The second (main) discharge trigger switches at the moment the triggering pulse arrives at input 26 provided that there is no charge on the capacitors 18 of the additional and first discharge triggers of the counter, i.e., when these triggers are in the state "1.

Subsequently, the counter is switched in the same way.

Outputs 29-32 are used to output information to external circuits.

Thus, with a relatively small power of the starting and reading pulses, reliable operation of the device is ensured.

Subject invention

A pulse counter in the Lre code, containing triggers of main and additional bits, performed on memory elements with non-destructive readout, for example, two transfluxors with windings, diode valves and capacitors, characterized in that, in order to transfer the power of the triggering and reading pulses, one from the output windings of each transfluxor is connected to a series-connected diode and a parallel-connected capacitor and resistor, with the junction points of 1k capacitors and resistors with output windings both transfluxors of each trigger are interconnected and form the transfer inputs of these triggers, and the connection points of the capacitors, resistors and diodes of the transfluxors of each trigger form the left and right transfer outputs of the triggers, respectively, which in each of the triggers of all the main digits of the counter start from the first one respectively, to the counting input and the transfer input of the trigger of the subsequent discharge, in the trigger of the additional discharge the indicated inputs are connected respectively to the transfer input and the mu Valid Trigger first main discharge, further discharge trigger carry input and connected to a counting input of this flip-flop and is connected to the bus starting pulse, the read coil and install triggers all the bits in the "null state are connected in series and are connected to respective inputs of the counter.