SU1725394A1 - Counting device - Google Patents

Abstract

The invention relates to devices for recalculating pulse signals and can be used in pulse signal processing devices, in digital measurement technology and specialized computing devices. The purpose of the invention is to enhance the functionality by allowing both the number of pulses to be counted and the intervals between them to be counted. The counting device contains the first 1 and second 2 counters, a clock pulse generator 3, elements 4, 5 and 12, a switch 6, drivers 7, 10 and 11, elements OR 8 and 9. Memory element 13, in which information is generated about the intervals between pulses, and the maximum address of meaningful information in the memory element determines the number of pulses. 1 il. (Ls

Description

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The invention relates to devices for converting pulse signals and can be used in devices for processing pulse signals, digital measuring equipment and specialized computing devices,

A counting device is known that contains a subtracting pulse counter, the information inputs of which are connected to the information inputs of the device.

It is also known to have a counting device containing first and second subtractive counters and a trigger, the direct and inverse outputs of which are connected to the enable inputs of the first and second pulse counters, respectively, whose information outputs are the information inputs of the counting device, and the subtraction inputs are connected to the input of the device.

The disadvantage of these devices is limited functionality, since these devices do not provide an estimate of the time interval between input pulses.

Closest to the proposed technical essence and the achieved result is a counting device containing the first and second counters, the clock generator, the first and second match elements, the switch and pulse driver, the transfer output of the first counter is connected to the first input of the first match element.

A disadvantage of the known device is the limitation of its functionality, since it does not provide for determining the duration of the interval between input pulses.

The aim of the invention is to extend the functionality by providing a count of the number of pulses and determining the duration of the intervals between them,

The goal is achieved by the fact that the first and second elements OR, the first and second elements are connected to the counting device containing the first and second counters, the clock generator, the first and second match elements, the switch and the pulse shaper, the transfer output of the first counter, are connected to the first input of the first match element, the first and second additional pulse shapers, a group of elements And, an element of RAM, informational inputs of which are connected to the outputs of the elements And, the first inputs of which are connected to the outputs n The first counter, the reset input of which is connected to the output of the pulse generator, the direct dynamic input of which is connected to the output of the first OR element, the first input of which is connected to the output of the first matching element, the direct dynamic input of the second counter,

the write / read enable input of the main memory element and the first input of the second matching element, the output and the second input of which are connected respectively to the forward dynamic

0 by the counting input of the first counter and the output of the clock generator, which is connected to the first input of the switch, the second input and output of which are connected to the input of the device and the second

5 by the input of the first match element, the third input of which is connected to the output of the second OR element, the first input of which is connected to the inverse enable input of the switch and the output of the first auxiliary pulse generator, the forward dynamic input of which is connected. with the address input of the switch, the device reset input, the second inputs of the AND elements and the inverse dynamic

5 by the input of the second additional pulse generator, the output of which is connected to the reset input of the second counter and the second input of the first OR element, and the information outputs and transfer output of the second

The 0 counter is connected to the address inputs of the RAM element and the second input of the second OR element.

The drawing shows a block diagram of the proposed device.

5 The counting device contains the first 1 and second 2 counters, the 3 clock pulse generator, the first 4 and the second 5 match elements, the switch 6 and the pulse shaper 7, the transfer output of the first counter 1 of the chip 1 is connected to the first input of the first match element 4. The device also contains the first 8 and second 9 elements OR, the first 10 and second 11 additional pulse formers, a group of elements AND 12, the element 13 of the RAM, whose information inputs are connected to the outputs of elements AND 12, the first inputs of which are connected to the outputs of the first counter 1 whose reset input

0 is connected to the output of pulse generator 7, the direct dynamic input of which is connected to the output of the first element OR 8, the first input of which is connected to the output of the first element 4 of coincidence,

5 direct dynamic input of the second counter 2, input of the write / read permission of the RAM element 13 and the first input of the second coincidence element 5, the output and the second input of which are connected respectively to the direct dynamic

the counting input of the first counter 1 and the output of the clock generator 3, which is connected to the first input of the switch 6, the second input and output of which are connected to the input 14 of the device and the second input of the first matching element 4, the third input of which is connected to the output of the second element OR 9, the first the input of which is connected to the inversion input of the resolution of the switch 6 and the output of the first additional generator 10 pulses, the forward dynamic input of which is connected to the address input of the switch 6, the input 15 of the device reset, sec and the inputs of the elements 1.2 and the inverse dynamic input of the second additional imaging unit 11 pulses, the output of which is connected to the reset input of the second counter 2 and the second input of the first element OR 8, and the information outputs and the transfer output of the second counter 2 are connected to the address inputs of the element 13 RAM and the second input of the second element OR 9.

The proposed counting device operates as follows.

The device is generally reset by applying an inverse pulse to input 15. The input pulses are fed to input 14. In the operating state, input 15 has a single logical signal that allows the inverse input signal to pass to the output of switch 6 and through element 4 to counting the input of the counter 2. With this the state of this counter is increased by one and the transition to the next address of the memory element 13 is provided. At the same time, the code from counter 1, which is an estimate of the interval between pulses, is written to the RAM at the starting address. This interval code is generated in counter 1 by counting the pulses from generator 3. When the input pulse arrives, the count stops as element 5 is turned off. In addition, after the end of the input pulse, the counter 1 is reset to its initial state by a signal from the driver 7 triggered at the end of the input pulse. If the counter 1 overflows during the time interval between the input pulses, the overflow signal from it switches the counter 2 to the next address. Thus, if in element 13 there are zero codes in several, for example, K, addresses, this means that the total number of pulses k at this moment (address is A) is AK, and the time interval between the last pulses is K 2n T + MT, where n is the size of counter 1; TP - the period of clock pulses, and M - the code in the counter 1, recorded in the element 13 after the group of K zero codes. When reset, the input switch is blocked, and the clock pulses arrive at counter 2, which provides the enumeration of addresses with the recording of zero codes generated by them at the outputs of the And 12 elements.

Thus, information on the number of input pulses and the intervals between them is collected, and due to the dynamic redistribution of memory, both a large number of pulses and large intervals between them are provided with a relatively small data gap in the element 13 and counter 1, which provides enhanced functionality of the device.

The reading of information from element 13 can be carried out in a reset mode or when implementing this element in a two-port scheme;

Claims (1)

The invention The counting device containing the first and second counters, the clock pulse generator, the first and second match elements, the switch and the pulse shaper, the transfer output of the first counter is connected to the first input of the first match element, so that , in order to extend the functionality by providing a counting of the number of pulses and determining the duration of the intervals between them, the first and second elements OR, the first and the second are also added to it. the second additional pulse formers, a group of elements I, an element of the operative memory whose information inputs are connected to the outputs, elements AND whose first inputs are connected to the outputs of the first counter, the reset input of which is connected to the output of the pulse former, whose forward dynamic input is connected to the output the first OR element, the first input of which is connected to the output of the first coincidence element, the forward dynamic input of the second counter, the write / read enable input of the memory element The first and the first inputs of the coincidence element, the output and the second input of which are connected respectively to the direct dynamic counting input of the first counter and the output of the clock generator, which is connected to the first input of the switch, the second input and output of which are connected to the input of the device and the second input of the first element match, the third input of which is connected to the output of the second OR element, the first the input of which is connected to the inverse pulse driver input, the output of which switch enable house and output connected to the second counter reset input the first additional driver and the second input of the first element OR, and pulses, direct dynamic input, co-information outputs and transfer output the second is connected to the address input of the comm-5 second counter connected to the address device reset input, the second inputs of the RAM element and inputs, elements AND and inverse dynamic second input of the second element OR. the second entry