SU1525889A1 - Device for monitoring pulse sequence - Google Patents

Abstract

The invention can be used in automation and computing devices or in monitoring periodic pulse sequences at various values of the follow-up period and the presence of gaps in the pulses. The aim of the invention is to expand the functionality of the device by ensuring the control of a series of pulses with a different follow-up period. The purpose of the invention is achieved as a result of the additional introduction of a second register and a second counter, a shift register, two delay elements, a second and third OR elements, an AND element, a group of AND switching elements, a decoder and a second code bus into the device. The diagram shows input 1, pulse shaper 2, trigger 3, elements OR 4 and 5, counter 6, delay elements 7 and 10, second counter 8, shift register 9, element 11, output 12, pulse generator 13, registers 14 and 17, the decoder 18, the group of switching elements AND 19, the elements OR 22 and 20, the outputs 21 and 22. The introduction of these elements and the connections between them provides control of the pulse skips in both continuous and discrete sequences of pulse series. 2 Il.

Description

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The invention relates to a pulse technique and can be used in automation and computer devices or in monitoring periodic pulse sequences at different values of the period. Investigation and the presence of gaps in the pulses.

The purpose of the invention is to expand the functionality of the possibilities by providing control of a series of pulses with different follow-up periods.

The goal is achieved through the additional introduction of a register, a counter, a shift register, two delay elements, an HSH11 element, an AND element, and a group of communicating I.I. elements.

FIG. 1 shows a block diagram of the device; in Fig „2 - the time diagram of the operation of the device for the case m 2,

The device contains input 1, shaper 2 pulses, trigger 3, elements OR 4 and 5, counter 6, delay element 7, counter 8, shift register 9, delay element Yu, element 11, output 12, pulse generator 13, register 14, code inputs 15 and 16, register 17, decoder 18, group of switching elements I 19, element ICH-20, outputs 21 and 22.

The time diagram (Fig. 2) shows the diagrams of the following signals: a) - pulses at input 1; b) - pulses at the second output of the imager 2; c) ig-shulsy at the first exit of the driver 2; d) - pulses on trigger 3; d) - pulses at the output of the counter 8; e) - pulses at the output of the delay element 7; g) - pulses at the output 21; e) - impulses in code 22; and) - pulses at the output 12.

Input 1 is connected to the input of the pulse driver 2, the first output of which is connected to the single input of trigger 3. The zero input of the latter is connected to the output of the OR 4 element, whose input is connected to the second output of the driver of the 2 pulses, input of the OR 5 element and the write input of the counter 6, the output of the element OR 5 through the delay element 7 is connected to the input of the record of the counter 8, the clock input of the shift register 9 and through the delay element Yu to the input of the element 11. The output of the counter 8 is connected to the input of the element OR 5 and the subtractive

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the input of the counter 6, the output of which is connected to the input of the element OR 4, the output of the device 12 and the reset input of the register 9, whose information input is connected to the single output of the trigger 3 and the input of the generator 13 pulses. The output of the latter is connected to the subtracting input of the counter 8, the information inputs of which are connected to the registers 14. The inputs of the latter are connected to the code inputs 15. The code inputs 16 are connected to the inputs of the register 17, the outputs of which are connected to the information inputs of the counter 6 and the inputs of the decoder 18. Same outputs decipheror 18 and shift register 9 are pairwise connected to the inputs of the corresponding elements of the AND 19 switching elements group whose outputs are connected to the inputs of the OR 20 element. The output of the latter is connected to the output of the device -keeping element 21 and the input 11 and whose output is connected to the output device 22.

The pulse shaper 2 generates a pulse at the second output when the leading edge of the input pulse arrives and at the first output - along the trailing edge of the input pulse. The pulse generator 13 is triggered when an upper level potential arrives at the input. Writing codes into the counters is done without pre-applying pulses to the reset input.

The input pulse sequence is formed by a series of pulses of duration t with an a priori unknown period of following T and an unknown number of pulses. The register 14 from the external measuring device records the binary code of the period T Ntg, where to is the period of the reference pulses of the generator 13. The pulses of the series under the influence of random factors may disappear. A number code (m + 1) is written to register 17 with input 16, where m is the maximum possible number of additional pulses. The number of outputs of the decoder 18 and shift register 9 is (2-1). The duration of the pauses between the series of pulses corresponds to the condition

T „b (t + 1) -T.

The controlled pulse sequence is fed to input 1 (Fig. 2, plot a). Impulses from the second exit

shaper 2 (Fig. 2, plot b) is set in the On trigger 3, write in the counter 6 code (t + 1) is not a delay tj - entered by the element

7, code T is written to counter 8. Pulses from the first output of driver 2 (Fig. 2, plot C) are set to 1 flip-flop 3 (Fig 2, plot d), which starts the generator 13, the reference pulses from the last output are fed to the subtracting input counter 8.

The overflow pulses of the counter 8 are generated only in the case of a series of pulse passes (Fig. 2, plot d), since when the input pulse arrives in the counter 8, the T code is recorded and terminated

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shift 1 of the lower bits of the register 9 in (w + 1) bit, skipping 1 through the previous elements And 19 is not made.

The duration and myca at output 21 corresponds to the duration of the skip. The pulses from the clock input of the shift register 9 are delayed by the time delay element 10. (where t is the shift and recording time in register 9) and arrive at the input of element 11. At output 22, the pulses appear with a delay (t + 1) T + t with respect to the first pass (Fig. 2, plot 3) and their the number corresponds to the number of missed pulses.

At the end of the series counter 8 ne

will generate an overflow pulse (fig, 2, plot and), indicating the end of the series. This pulse sets in O the trigger 3 and the register 25, If the input sequence of pulses is continuous, at the output 12 no pulses are generated. In the case of gaps, pulses are formed at the outputs 21, 22.

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the arrival of reference pulses, Impul-20 replenishes (t + 1) times and the overflow counter 6 records the code T in counter 8 and goes to the account in counter 6, which does not have time to overflow with gaps, since it contains the code (t +1). The latter is rewritten from register 17 with each input pulse.

The sequence of pulses on the output of delay element 7 (Fig 2, plot e) is formed by a sequence of overflow pulses and a sequence of pulses from the second code of the former 2. The number of pulses in this sequence is greater than the number of pulses of the input series by (ha + 1). The pulses of this sequence are applied to the clock input of the shift register 9.

With gaps, trigger 3 remains in one state until the next pulse of the series arrives. Therefore, in shift register 9, a right shift is made for one bit and 1 is written to the low-order bit. If there are no gaps in shift register 9, the right digit is shifted by one bit and O is written to the lower bit, 1 by (t + 1 ) the output of register 9 by pos 35

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Thus, the use of the proposed device makes it possible to monitor the pulse passes both in continuous sequences and in sequences of pulse series. At the same time, after the end of the pulse train, the false pulse skip detection signals are not generated.

Claims (1)

Invention Formula A device for controlling a pulse sequence containing a pulse shaper, the input of which is connected to the input of the device, and the first output - to a single input of a trigenera, the output of which is connected to the input of a pulse generator, the output of which is connected to the subtractive input of the first counter, the information inputs of which are connected to the outputs of the first register, the inputs of which are connected to the first code buses of the device, the output of the first counter is connected to the first input of the first OR element, the second input of which is connected to The output of the pulse generator, characterized in that, in order to expand, the time (tT t) after the first pass (at m 2), 1 is formed at the third output of the register 9 (FIG. 2, plot g) after a time (2T - t .). 1 s (t +1) of the output of register 9 is passed by (t + 1) element I 19 to exit 21, since the other input of this element is fed 1 s (t + 1) of the output of the decoder 18, the remaining outputs of which have O, Therefore, when will generate an overflow pulse (fig, 2, plot and), indicating the end of the series. This pulse sets the trigger 3 to O and the register 9. If the input pulse sequence is continuous, no output pulses are generated at output 12. In cases of gaps, pulses are formed at the outputs 21, 22. replenishes (t + 1) times and counter 6 thirty 35 40 45 50 55 Thus, the use of the proposed device makes it possible to monitor pulse passes both in continuous sequences and in sequences of pulse series. At the same time, after the end of the pulse train, the false pulse skip detection signals are not generated. Invention Formula A device for controlling a pulse sequence containing a pulse shaper, the input of which is connected to the input of the device, and the first output - to a single input of a trigenera, the output of which is connected to the input of a pulse generator, the output of which is connected to the subtractive input of the first counter, the information inputs of which are connected to the outputs of the first register, the inputs of which are connected to the first code buses of the device, the output of the first counter is connected to the first input of the first OR element, the second input of which is connected to orym output of the pulse shaper, characterized in that, in order to expand functional 715 capabilities by providing control over a series of pulses with different follow-up periods, the second register and counter, the shift register, two delay elements, the second and third OR elements, the AND element, the group of switching elements AND, the decoder, the second code buses, and the second the output of the pulse former is connected to the first input of the second element OR and to the recording input of the second counter, the subtracting input of which is connected to the output of the first counter, the output of the first element OR through the first element aderzhki connected to the recording input of the first counter, with the clock input of shift and vhodom.registra second delay element whose output is connected to the first input element 0 889 five 0 eight And the output of which is connected to the first output of the device, the second code buses of the device are connected to the inputs of the second register, the outputs of which are connected to the inputs of the decoder and to the information inputs of the second counter, the output of which is connected to the second output of the device, and the reset input of the shift register, the information input of which is connected to the trigger output, the same name outputs of the decoder and the shift register are pairwise connected to the inputs of the corresponding elements And, a group of switching circuits The elements And, the outputs of which are connected to the inputs of the third element And, the output of which is connected to the second departure of the element And and the third output of the device,