SU1238062A1 - Multiplying-dividing device - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in specialized computers of automatic control systems. The purpose of the invention is to increase the speed and reliability of operation by issuing a signal about the end of the calculations, which allows only the result of the completed calculations to be calculated. The device additionally introduced a signal bus on the completion of calculations and much simpler and reliable elements 2 Il. ISD 00 SH) o :) to

Description

The invention relates to automation and computing and can be used in specialized computer systems for automatic control.

The purpose of the invention is to increase the speed and simplify the device.

FIG. 1 shows the functional electrical circuit of the multiplier-separating device; in fig. 2 - functional electrical circuit of two-channel code-frequency converter ..

The multiplier-separating device contains a two-channel converter 1-code - frequency, element 2, to the input of which the first output of two-channel converter 1 is connected - code - frequency, divider 3. frequency, the input of which is connected to the output of element 2, counter 4 to the subtractive input of output divider 3 frequency is connected, delay element 5, element 6, the input of which is connected to the second output of two-channel converter 1 code - frequency 1, element 7, frequency divider 8, input of which is connected to output 6 of element 6, counter 9 to the sums The output of which is connected to the output of the frequency divider 8, and to the reset input is the output of the AND 7 element, AND 10, the input of which is connected to the output of the delay element 5 and with the input of the AND 7 element, the OR element, whose input is connected to the output of the AND element 10, and the output -.c with the enable input of recording information in parallel form of the counter 4, bus 12 divider, which are connected to the first group of inputs. a two-channel converter 1 code frequency, tires 13 of the first multiplier are connected to the second group of inputs of a two-channel converter 1 code-frequency, buses 14 of the second factor that are connected to information inputs of counter 4, start bus 15, which is connected to the input of the element OR 11, bus I6 mode control, which is connected to the input element And 10, the bus 17 alarm, which is connected to the input element

5 delay, with the inputs of the elements And 2,

6 and 7 and with the overflow output when subtracting the counter 4, the output tires 18-1., 18.2, o..18 are the results to which the outputs of the counter 9 are connected,

Dividers 3 and 8 frequencies are t-bit binary counters.

ki performing averaging of non-uniform pulse sequential -;

exits

from first f and second f

a two-channel converter 1 code-frequency (these sequences are averaged no less than a hectare).

Counter 4 on the subtracting and counter 9 on the summing inputs operate from the leading edges of the pulses arriving at these inputs. At the output of the overflow during the subtraction of counter 4, the signal appears in the case if the contents of counter 4 are equal to 0 and if there is no pulse at the subtracting input, i.e. the signal appears at the moment of the end of the pulse recorded in the counter 4 the number O. When the pulse arrives at the input of the recording of information in the counter to the counter 4, the code is stored at its information inputs. When there is a signal at the reset input of the counter 9, the latter is in the zero position regardless of what signals act on its remaining inputs.

The magnitude of the time delay element. This 5 delay is chosen sufficient for. reading the result from the output bus 18-1, 18-2, ..., 18-k, but not more than half the minimum pause between the pulses from the output of the divider 3 frequencies, i.e. not more than 0.5-2 (f) f

 X mlx max

The divider and multiplier codes must be on the corresponding tires for the entire calculation time. A start pulse is applied to the start bus 15: the duration is as follows: - to be sufficient to record the code from the bus 14 to the counter 4 o A single signal is given to the bus 16 if the device is to operate in cyclic mode, and a zero signal if the device is to operate in one-time account about

A pulse is applied to the bus 17, the duration of which is equal to the sum of the delay time of the delay element 5 and the response time of the elements AND 10, OR 11 and the counter 4 "

-

The two-channel code to frequency converter 1 (FIG. 2) contains reference pulse generator 19, elements 55 OR 20, 21, element 22, counter 23, code comparison block 24, code comparison block 25, the first group of inputs of which is connected to the first group

3

sing the inputs of the block 24 and with the information outputs of the counter 23, the trigger 26, to the S-inlet of which the output of the block 24 is connected, the trigger 27, the S-input of which is connected to the output of the block 25, element I 28, to the input of which the output of the trigger 26 is connected, R - whose input is connected to the R-input of the trigger 27 and to the overflow output when summing the counter 23, the element 29 whose input is connected to the input of the element 28, the output of the generator 19 and the summing input of the counter 23, the reset input of which is connected to the output of the element And 22, with the input element And 28, with the input element And 29, to another the input of which is connected to the trigger output 27, buses 12 are connected to the inputs of the OR 20 element and to the second group of inputs of block 24, buses 13 are connected to the inputs of the OR 21 element and to the second group of inputs of block 25, the output of the And 28 element is connected to the first input of the two-channel converter 1 code is the frequency, the second. Input of which is connected to the output of element AND 29. Counter 23 on the summing input operates from the leading edges of the pulses arriving at this input. If there is no signal at the reset input, the counter 23 is in zero-. irrespective of the presence of signals at its other inputs. The output of the overflow during summation appears in the event that all bits of the counter 23 are in the unit position and if the pulse at the summing input of the counter 23 has expired.

Blocks 24 and 25 give signals to their outputs if the codes on their first and second groups of inputs are equal. In the absence of codes or on tires 12 or on tires 13, the counter 23 is held in the zero position.

The multiplier-dividing device works as follows

In the initial state, in the absence of codes on buses 12 and 13 at the output of the elements OR 20 and 21 there are no signals, at the output of the element And 22 there is also no signal and counter 23 and the triggers 26 and 27 are kept in the zero position, elements 28 and 29 are closed from - due to the absence of a signal at the output element And 22.

When the divider and first multiplier codes are given, the signals appear

062

four

at the outputs of the elements OR 20 and 21 and resets the element AND 22, allowing the counter 23 and the triggers 26 and 27 to work and opening the elements 28 and 29, the counter 23 begins to sum the pulses of the generators 19 that pass through the elements 28 and 29 to the first and the second outputs of the converter 1. At the moment when the contents of the counter 23 become equal to the divider code or the first multiplier code, one of the blocks 24 or 25 is triggered and sets the signal from its output to the single position corresponding to the first trigger 26 or 27, while closing corresponding element nt AND 28 or 29 and the arrival of pulses is stopped at the corresponding input. At the moment when the contents of counter 23 become equal to another code, the skip of generator I9 pulses to the other output of converter 1 stops. When a signal appears at the overflow output when adding counter 23, triggers 26 and 27 are set to zero, opening elements 28 and 29 , and pulses are output to the outputs of the converter 1, the converter 1 operates in this way until the divisor or the first factor is cleared. As soon as at least one of the codes is cleared, the signal at the output of the corresponding IL 20 or 21 element disappears and, consequently, at the output of the AND 22 element, And 28 and 29 elements are closed, the triggers 26 and 26 and the counter 23 are set to zero. i.e. converter I will return to the initial state.

In the initial state, the counter 4 is in the zero position, at the output of the overflow when subtracting the counter 4 there is a signal that closed the elements And 2 and 6, at the output of the element And 7 there is a signal holding the counter 9 in the zero position on the tires 12-16 no signals

At the time of the codes on buses 12 and 13, the two-channel converter 1 begins to generate code-frequency pulses at its first output with frequency f КХ, where / К is the proportionality factor, and at its second output pulses

With frequency fi KY.

uh

Before starting the calculations, the buses 13, 14 and 12 are given the codes of the first factor, the second factor and the divider respectively, a single signal is sent to the bus 16 if the device should operate in cyclic mode, and a zero signal if the device should work in single-count mode .

Calculations begin when a trigger pulse is applied to the bus 15. The start pulse from bus 15 through the OR 11 element is fed to the input of information recording permission in parallel view of counter 4, the code of the first multiplier Z is recorded in counter 4, the signal disappears at overflow output when counter 4 is subtracted, and counter 9 is opened 2 and 6, through which the frequency pulses start to pass, respectively, f and f to the inputs of dividers 3 and 8 of the frequency C of the output of the frequency divider; frequency pulses

f f, - jt are fed to the subtracting input.

counter 4, ac output divider 8

frequency pulses of frequency f

 fy

g 2

arrive at the summing input of the counter 9. At the moment of termination of the pulse from the output of the divider 3 frequencies recorded in the counter. 4, the number 0, a signal appears at the output of the overflow of counter 4, elements 2 and 6 are closed, element 7 is prepared for opening, delay element 5 is triggered, and a signal about the end of one calculation cycle is sent to bus 17 t a signal appears at the output of the 5.delay element, the element And 7 triggers and the signal from its output sets the counter 9 to the zero position (for T, the calculation result must be read. In addition, the signal from the output of the delay element 5 goes to the control element And 10, and if devices find a single axle counting mode on the bus 16 has a zero signal, the AND gate 10 is not activated and the device remains in the original state before the arrival of the trigger pulse sledzto- present ,, if the apparatus is in cyclic mode, the AND gate 10 is activated L

the signal from its output is fed to the input of the information recording resolution in parallel form of counter 4, in which the first code is written

the inhabitants are t, and the calculation cycle is repeated ..

The result, the number N, recorded in counter 9 at the moment of the end of the calculations, is equal to N t. / T, where t is the time that counter 4 is in a position other than zero; 1 - period of pulses at the output of the splitter 8 frequency. Time t is ZT. where T is the period of the pulses at the output of the divider 3 frequency. Then

N

rm, t „

10 15 20

five

0

0

S

five

0

Claims (1)

Invention Formula A multiplying-dividing device containing a two-channel code-frequency converter, the first And element, the first frequency divider, the first counter, to the subtractive input of which the output of the first frequency divider is connected, the second And element, the first input of which is connected to the second output of the two-channel code-frequency converter, the second frequency divider, to the input of which the output of the second element I is connected, the second counter, the summing input of which is connected to the output of the second frequency divider, the input buses of the device divider are connected The first group of inputs of the two-channel code-frequency converter, the input buses of the first factor of the device are connected to the second group of inputs of the two-channel code-frequency converter, the outputs of the second counter are connected to the output buses of the device, characterized in that, for speed and simplification, it contains the element, g of the delay, the third and fourth elements AND, and the element OR, whose code is connected to the input of the resolution of the information record in the parallel form of the first counter, the information the inputs of which are connected to the tires of the second device multiplier, the device launch bus is connected to the first input of the OR element, the second input of which is connected to the output of the fourth element AND, to the first input of which the device control mode bus is connected, the second input of the fourth And is connected to the second input of the third element And to the output of the delay element, the input of which is connected to the overflow output of the first counter, to the first input of the first element And, to the second input of the second element And, to the signal bus of the device and to the first input of the third element And, the output of which is connected to the reset input of the second counter, the first output of the two-channel code-frequency converter is connected to the second input of the first element AND, the output of which is combined with the frequency divider. 12 bo J8-K ( Compiled by B. B. Berezkin Editor M. Tovtyn Tehred M. Khodanych Proofreader. V. But ha 3292/49 Circulation 671 Subscription VNIIPI USSR State Committee on affairs of inventions and discoveries P3035, Moscow, Zh-35, Raushsk-nab. 4/5 Production and printing company, Uzhgorod, st. Project, 4 ui.2