SU1718223A1 - Computer faults simulator - Google Patents

Abstract

The invention relates to digital computing and can be used in the development of systems for monitoring and diagnosing computing devices. The purpose of the invention is to enhance the functionality by providing a simulation of both permanent and moving faults. At the moment of occurrence, the fault and its duration are considered random variables distributed exponentially with specified expectation values. 1 il.

Description

The invention relates to digital computing and can be used to simulate computer malfunctions.

A device for simulating computer faults is known, which contains three registers, a trigger, two comparison blocks, a clock counter, the AND element, and a pulse shaper.

A disadvantage of this device is the inability to change the time of action of a signal simulating a malfunction.

The closest in technical essence and the achieved positive effect is a device for simulating computer faults, containing four registers, three comparison blocks, two triggers, a clock counter, a pulse shaper, a delay element, and an element I.

The object of the invention is to expand the functionality of the device by simulating both persistent and intermittent faults.

The drawing shows a block diagram of the device.

The device contains input 1 for setting computer command codes, synchronization input 2, input 3 for control signals, registers 4-11, comparison blocks 12-15, triggers 16 and 17, counters 18 and 19 ticks, driver 20 pulses, delay element 21, and element 22-24, the group of elements And 25, the element And 26, the sensor 27 uniformly distributed random numbers (DRRSCH), block 28 nonlinearity, block 29 elements NOT, blocks 30 and 31 multiplication, elements NOT 32 and 33, elements 34-36 delay, element OR 37, output 38 of the device.

To simulate intermittent faults, the time of occurrence and the duration of which (as well as permanent faults) are distributed exponentially, it is necessary that the device for simulating computer faults additionally performs the following functions: simulates random variables distributed exponentially with a given mathematical waiting; imitated a specified number of faults.

with

with

with

GO SO

In order to obtain exponentially distributed random numbers, it is necessary to obtain uniformly distributed numbers in the interval 0, 1. Such a number is obtained at the output of the HSPCH (P is uniformly distributed in the interval O, 1 is a random quantity).

To obtain from the uniformly distributed random numbers exponentially distributed, you need to perform a transformation

(P)

where Y is a random variable distributed exponentially with an expectation equal to M.

The production of an exponentially distributed quantity is performed using a nonlinearity block 28, which implements the conversion

(P), where P - takes a value in the interval 0,

eleven

element NOT 29 and blocks 30 and 31 multiplied by

with registers 9 and 10, and in register 9 the mathematical expectation of the moment of the occurrence of the malfunction is entered, and the register 10 is the mathematical expectation of the duration of the malfunction.

To simulate a specified number of faults, a 19 clock counter is used, which counts the number of fault simulations by the number of trigger settings 16 in one state. Comparison unit 15 generates a enable signal if the number of trigger settings 16 in one state is not greater than the number recorded in register 8.

A device for simulating computer malfunctions works as follows.

In preparing the device for operation, the input of the register 4 is connected to the chain of transmission of computer commands, and element 26 (input 2) is connected to the generator of the clock frequency of the computer. The third input 3 of the device is connected to the control signal bus, the arrival of which causes a change in the code at input 1. Output 38 is the output of the device and is connected to the point of the circuit where it is necessary to simulate a fault. In the initial state, registers 4, 6, 7 and 11, counter 18 and 19 are in the zero state, triggers 16 and 17 are in the O state. In register 5 the command code is entered, in register 8 the number of faults that are necessary It is necessary to simulate, in register 9 - the mathematical expectation of the moment of the occurrence of a malfunction, in register 10 - the mathematical expectation of the duration of the malfunction (the chains of installations are not shown).

When the program is executed at a certain point in time, a code similar to the code in register 5 is entered into register 4, a signal appears at the output of comparator 12, which sets trigger 16 to state 1. Clock counter begins to count the number of trigger settings 16 to one . In block 15, the number of trigger settings 16 is compared to one with the number of faults that need to be simulated. The delay element 36 is necessary to take into account the time of passage of the signal from element 23 to block 15. If the number of trigger settings 16 is not greater than the number of faults recorded in register 8, then comparison block 15 generates an enable signal that enters the input of element 24 on the second the input of which receives a signal from the output of the trigger 16.

The permissive signal from the output of the element 24 goes to the element 32, the signal from the output of which closes the element 23. The permissive signal from the output of the element 24 goes to the input of the DPR4 27, the delay element 34 and the element 26 through which the clock pulses go to the counter 18 cycles, which counts the number of pulses. The DPRS4 27 generates uniformly distributed random numbers that are recorded by the enable signal from the delay element 34 to register 11 and fed to the nonlinearity block 28 and through the block of NOT elements 29 to the multiplication blocks 30 and 31, the values of which are received from the registers 9 and 10 respectively.

From multiplication unit 30, the value corresponding to the moment of the occurrence of the malfunction is written to register 6, and from multiplication unit 31 to the register 7, the value corresponding to the duration of the malfunction according to the enabling signal from delay element 35. As soon as the contents of the counter 18, the one that seems to be greater than or equal to the value in the register 6, at the output of the comparison unit, a signal appears that sets trigger 1, the output of which through the element NOT 33 closes the element 25, through which the unit 13 comparisons to the elements And group 25 received an enable signal. In addition, the signal from the output of the comparison unit 13 through the elements of OR 37 and the delay 21 triggers a counter of 18 cycles.

Allowing a single signal from the output of the trigger 17 is fed to the imaging unit 20 pulses, which begins to produce pulses. In addition, the enable signal from the trigger 17 is fed to

the input element And 22, the permissive signal from the output of which is fed to the control input of the unit 14 of the comparison, which always works after the operation of the block 13 of the comparison. When the comparator unit 13 operates, the control signal from its output through the elements OR 37 and the delays 21 resets the 18 clock count to the zero state. At the same time, this signal sets to 1 trigger 17. A single signal from trigger 17 through the elements HE 33 and AND 25 prohibits comparing the counter values to 18 ticks and register 6 in comparison block 13. At the same time, this signal allows AND 22 to compare the contents of the register 7 and the 18-beat counter. The operation of the comparison unit 14 occurs when the contents of the 18-clock counter are greater than or equal to the contents of the register 7.

After that, the signal from the output of the comparator unit 14 through the OR element 37 and the delay 21 counter 18 clock cycles is again reset to the zero state and the device is ready to repeat the operation cycle, since the trigger 17 is set with the same signal to the O and allows information to pass through the AND element 25 to block 13 comparison. .

When imitating the next fault, the device works in the same way, and the 18 clock counter starts counting only after the arrival of the corresponding command code in register 4, operation of the comparison unit 12, trigger 16, comparison unit 15, opening of the AND 24 and 26 elements. 27 and the calculation of the new values of the beginning and duration of the fault. Comparison unit 13 is always triggered before comparison unit 14, since comparison unit 14 can only work after its control input through trigger 17 and the AND element 22 from comparison unit 13 receives an enable signal. Moreover, after the comparison unit 13 is triggered using the group of elements AND 25, the element NE 33 and the trigger 17, the connection between the 18 clock counter and the comparison unit 13 is broken, which is restored when only the next fault is simulated.

If the device simulates the already specified number of faults recorded in register 8, then after the next match of the command codes at the output of the comparison unit 15, the enabling signal is not generated, the And 24 element is always closed. The operation of the device ends there.

Ф орм ул а and з о б р ё te n and

A device for simulating computer faults, containing four registers,

three comparison blocks, two triggers, the first clock counter, the first delay element, the pulse shaper and the first AND element, the information input of the first register being the input for setting the command code, the first and second information inputs of the first comparison block are connected to the outputs of the first and second registers, respectively , output Equal to the first unit of comparison is connected to a single input

the first trigger, the first group of information inputs of the second comparison unit — with the output group of the third register; the control input of the third comparison unit — with the output of the first element I; the first and second information inputs of the third unit

5 comparisons with the outputs of the first clock counter and the fourth register respectively, the output is equal to the second comparison block - with the single input of the second trigger, the output of the first delay element - with the reset input of the first clock counter, the output of P0 of the third comparison block - with zero inputs of the first and second the flip-flops, the output of the second flip-flop is with the first input of the first element AND and the input of the pulse former, the output of which is the output of the device, characterized in that

5 the goal of extending the functionality by providing simulations of both constant and intermittent faults, a sensor of uniformly distributed random numbers, with

0 fifth to eighth registers, second and third elements AND, second clock counter, AND group of elements, second to fourth delay elements, fourth comparison block, nonlinearity block, two blocks

5 multiplications, three elements NOT, a block of elements NOT, an element OR, and the output of the first trigger is connected to the counting input of the second clock counter, the output of which is connected to the first information input

0 of the fourth comparison block, the second information input of which is connected to the output of the fifth register; the output Equals the fourth comparison block connected to the first input of the second element I, the second input of which is connected to the output of the first 5 trigger, the output of the second element I to the first input of the third element I, the input of the second delay element, the input of the first element NOT and the control input of the sensor of uniformly distributed 0 random numbers, the output of the first element NOT with the first input of the fourth element I, the second input of which is channeling yuschim input device, the fourth output element and - with the input resolution of the first comparator block, with the input of a first recording

register and through the third delay element with the resolution input of the fourth comparison unit, the clock input of the device is connected to the second input of the third element AND, the output of which is connected to the second input of the first element And, to the synchronous input of the second comparison unit, to the counting input of the first clock counter, output the sensor of uniformly distributed random numbers is connected via an eighth register with an input of a nonlinearity block, the output of which is connected to the input of a block of elements NOT, the output of which is connected to the first and second inputs of blocks multiplied and, the second inputs of which are connected to the sixth and seventh registers, the outputs of the first and second multiplication blocks - with the information inputs of the third and fourth registers, the output of the second trigger through the second element NOT - with the first inputs of the first corpses

And the second inputs of which are connected to the corresponding bit outputs of the first clock counter, the outputs of the elements of the first group to the second group of information inputs of the second comparison block, the output of the third comparison block

- with the reset inputs of the first, third and fourth registers and the first input of the OR element, the output of the second delay element

- with the control input of the eighth register and the fourth delay element with the control inputs of the third and fourth registers, respectively, the second input of the OR element is connected to the output of Equal to the third comparison unit, the output of the OR element - with the input of the first delay element, the output of the first AND element - with synchronous input of the third unit of comparison.

Claims (1)

Claim A device for simulating computer malfunctions, containing four registers, three comparison units, two triggers, a first clock counter, a first delay element, a pulse shaper and a first element 14, the information input of the first register being an input for setting a command code, the first and second information inputs of the first block comparisons are connected to the outputs of the first and second registers, respectively, the output is equal to the first comparison block is connected to a single input of the first trigger, the first group of information inputs of the second block equalities with the group of outputs of the third register, the control input of the third comparison unit - with the output of the first element And, the first and second information inputs of the third comparison unit - with the outputs of the first cycle counter and the fourth register, respectively, the output is equal to the “second comparison unit - with a single input of the second trigger , the output of the first delay element is with the reset input of the first clock counter, the output is equal to the third comparison block with the zero inputs of the first and second triggers, the output of the second trigger is with the first input of the first element And and the input of the pulse shaper, the output of which is the output of the device, characterized in that, in order to expand the functionality by providing a simulation of both constant and intermittent faults, a sensor of uniformly distributed random numbers, from fifth to eighth registers, is introduced into it and third elements 14, second clock counter, group of elements 14, second to fourth delay elements, fourth comparison block, nonlinearity block, two multiplication blocks, three NOT elements, element block in NOT, an OR element, wherein the output of the first trigger is connected to the counting input of the second clock counter, the output of which is connected to the first information input of the fourth comparison unit, the second information input of which is connected to the output of the fifth register; the output is equal to the fourth comparison block is connected to the first input of the second AND element , the second input of which is connected to the output of the first trigger, the output of the second element And - with the first input of the third element And, the input of the second delay element, the input of the first element NOT and the control input a uniformly distributed random number sensor, the output of the first element is NOT with the first input of the fourth element And, the second input of which is the control input of the device, the output of the fourth element is with the enable input of the first comparison unit, with the input of the first register entry and through the third delay element with the input resolution of the fourth block of comparison, the clock input of the device is connected to the second input of the third element And, the output of which is connected to the second input of the first element And, with the clock input of the second block of comparison, with about the counting input of the first clock counter, the sensor output of the evenly distributed random numbers is connected through the eighth register with the input of the nonlinearity block 10, the output of which is connected to the input of the block of elements NOT, the output of which is connected to the first and second inputs of the multiplication blocks, the second inputs of which are connected to the sixth and Seventh 15 registers, the outputs of the first and second blocks of multiplication - with information inputs of the third and fourth registers, the output of the second trigger - through the second element NOT - with the first inputs of the first corpse - 20 elements in And, the second inputs of which are connected to the corresponding bit outputs of the first clock counter, the outputs of the And elements of the first group - with the second group of information inputs of the second comparison unit, the output of the third comparison unit - with reset inputs of the first, third and fourth registers and the first input of the OR element, the output of the second delay element - with the control input of the eighth register entry and through the fourth delay element with the control inputs of the third and fourth register entries, respectively, the second input of the OR element is connected to the output of the Third comparison block, the output of the OR element is connected to the input of the first delay element, the output of the first AND element is s sync input of the third block comparison. Compiled by A. Sirotskaya Editor I. Schull .Techred M. Morgenthal Corrector I. Muska Order 882 Circulation Subscription VNIIIPI of the State Committee for Inventions and Discoveries under the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Combine Patent, Uzhgorod, 101 Gagarin St.