SU1509901A1 - Arrangement for monitoring digital devices - Google Patents

Abstract

The invention relates to computing and can be used to simulate information packages in the process of setting up, monitoring and diagnosing digital device faults. The device contains a multiplexer, a counter, a memory block, a group of elements And, a modulo two adder and a shift register. The purpose of the invention is to reduce the hardware cost of the device and is achieved by introducing a comparison unit, an NAND element and a pulse shaper into it. The simulated information is formed from a sequence of pseudo-random codes generated by a shift register with a modulo-two adder in feedback, by sifting out forbidden combinations. The screening is carried out according to the program stored in the memory block by modifying with the aid of a group of elements AND of the feedback structure of the pseudo-random code generator at the moments when it forms certain codes defined by the program and detected by the comparison block. 3 il.

Description

The invention relates to computing and can be used to simulate information signals at the inputs of digital devices during their autonomous tuning, performance testing and diagnostics of irregularities.

The aim of the invention is to reduce hardware costs and expand the class of tasks of the device by providing better simulated information with blocks of arbitrary length.

Figure 1 shows the functional diagram of the device for simulating information channels; 2, timing diagrams for the operation of the device,

In tab. 1 and 2 are examples of simulated information sequence.

The device contains (Fig. 1) multiplexer 1, counter 2, memory block 3, comparison block 4, AND-NE element 5, modulator two modulo 2, And 7-1-element group, 7-k, shift register 8, driver 9 pulses ,. synchronous input 10, control input 11, recording input 12, information inputs 13, information output 14, and setup input 15. The number of AND elements 7 in the group is determined by the number of registers

;about

(UD

31509

Pa 8 needed for organizing, in addition to the main, additional feedback in a pseudo-random sequence generator (UCS), built on the basis of shift register 8 with adder 6 modulo two in feedback. In Fig. 1, k 6, which makes it possible to form p-bit (Fig. 1,) sequences with forming polypomas

R. (x) x +1;

) x ° + x + 1;

RE (x) x + x + 1;

) x 5 + +1.

The multiplexer 1 contains the element NOT 16 and the element AND-OR-NOT 17 (figure 1).

The device works in the following way.

The formation of information signals for monitored objects is based on programmable sifting of forbidden combinations of a sequence of codes obtained using the UCS generator for ease of the shift register 8 with modulator 6 modulo two in feedback. By changing the UCS feedback structure one or several cycles before the appearance of forbidden code combinations.

Before starting work to bring the device back to its original state, a pulse is given to the setup input 15. At the same time, the initial code pattern is written to the shift register 8, and the counter 2 is zeroed. Then, the selection program is loaded into memory block 3, which determines the structure of the output sequence of information signals, and, in particular, the code combinations that will be excluded from the generated code sequence, the selection program consists of (n + 1) - bit instructions. The group of bits B1 - Bp of each instruction determines the n-bit code combination that is formed at the outputs of shift register 8 one or more cycles prior to the appearance of the forbidden code and at which the feedback is changed to the CSI generator. Bit C, - C, C instructions determine the feedback structure of the UCS generator until it reaches the code combination specified in Bit B1 - Bp of the same instruction. When loading the selection program to the control input 11, a logical O signal is given,

g

five

0 5 0

5 40 5 0

The loading mode, for informational inputs 13, is the code of the first instruction, and, at entry 12 of the record, a negative follow pulse. The impulse writes the first instruction of the program to the zero cell of the memory block 3. On the pulse front of it, the pulse shaper 9 generates a negative pulse, which is fed through multiplexer 1 to the counting input of counter 2. On the leading edge of this pulse, the contents of the counter

2 is increased by one. Similarly, the remaining instructions of the programs are loaded into memory block 3. When the loading of the pulse selection program is over the setup input 15, the counter 2 is zeroed. A logical 1 signal is applied to the write input 12, which determines the reading mode for the block

3 Mom tees At control input 11, a logical 1 signal is set, which sets the mode for simulating information signals. The synchronous input 10 is supplied with clock pulses.

Consider the work on the example of forming a fragment of the output code sequence (Fig. 3).

Suppose that code combinations, 000100001110000 and 101001000011 are forbidden for the object being monitored. In the initial state in the shift register 8, the initial combination 100001110000000 is written, the counter 2 is reset and the output of the selection program is set to the memory block 3, To the adder 6, only the 14th and 15th bits of the shift register 8 are connected, i.e. in the PSK generator, feedback is defined, which is described by the generator polynomial P (x) x + X 4- 1. At the falling edge of each clock pulse at sync input 10, the PSK generator generates another code arriving at the information outputs 14. The comparison unit 4 performs Comparison of the code in the 8 shift register outputs with the code set at the B1 outputs - B15. 3 memory block. In the third cycle of operation, a logical 1 signal is generated at the output of the comparison unit 4, indicating that the compared codes are the same. At the fourth cycle, at the output of the NAND element 5, a negative pulse is generated, which, through multiplexer 1, arrives at the counting input of counter 2 and increases its content by one with its leading edge. The outputs of memory block 3 are set by the second instruction of the information signal simulation program. In this case, bits C - C, instructions provide connection to the adder of 6 3,12,14 and 15 bits of the 8 shift register, i.e. PSK generator

clock and installation inputs of the device, different

20

tunes to the formation of a pseudo output and the information input of a random sequence from the shift processor, the synchronous input and the input by the resetting polynomial RH. (X) x +1. which are respectively on the falling edge of the fourth clock pulse at the information outputs

14, the first code appears after this, in order to reduce the hardware. Thus, the emitted model code combination 000100001110000, which was to be formed on the fourth clock pulse with the forming polynomial P (x), will be skipped.

After the fourth clock cycle, the information outputs 14 receive the sequence of the CLAIM with the forming polynomial PJ (x). After the seventh cycle, the comparison unit 4 fixes the equality of the codes at the outputs of the shift register 8 and B 1 - B15 of the memory block 3. With the arrival of the next clock pulse, a change occurs in the PSK generator of the generating PZ polynomial (x) by P ,. (x) x + + x + X + 1, thereby bypassing the prohibited code of the device’s combinatorial expenditures, a comparison block, a pulse shaper and a Pi-HE element are inserted into it, the first information input of the multiplexer is connected to the output of the NAND element, the first input is connected to the clock input of the device, and the second input is connected to the output of the comparator unit, the first and second groups of informational inputs of which are connected respectively to the output group of the shift register and the first group of output memory units whose recording input is input device B and is connected

30 through the pulse shaper with the second information input of the full-lens, the second group of inputs of the modulo adder two is connected to the outputs of the elements of the AND group, the first and second

the input of the device operation mode, the memory block, the information and address inputs of which are connected respectively to the command input of the device and the output of the counter, the group of elements AND and the modulo two, the first group of inputs and output of which are connected respectively to the group

the outputs and information input of the shift register, the synchronization input and the reset input of which are respectively

clock and installation inputs of the device, different

the outputs and information input of the shift register, the synchronous input and the reset input are respectively

in order to reduce the number of

in order to reduce the number of

unit cost, a comparison unit, a pulse shaper, and a Pi-HE element are inserted into it, the first information input of the multiplexer is connected to the output of the NAND element, the first input connected to the clock input of the device, and the second input to the output of the comparison unit, the first and second groups of informational inputs of which are connected respectively to the group of outputs of the shift register and the first group of outputs of the memory block whose recording input is the recording input of the device and connected

through the pulse shaper with the second information input of the full-lens, the second group of inputs of the modulo adder two is connected to the outputs of the elements of the AND group, the first and second

100101001000011. Next, the form of the inputs of which are connected to the corresponding information signals is continued to the second group of outputs of the memory block and the group of outputs of the shift register, the counting input and the reset input of the counter are connected respectively to the output. 40 of the multiplexer and the setup input of the device, the output register group of the shift register is informational. a group of device outputs.

Claims (1)

similarly. Invention Formula A device for controlling digital devices, comprising a multiplexer, the control input of which is Table 1 Table 2 FIEL Sin) 1roimp1 / Asa nabmde 10 Codes bymdah  Ja..l Exit CodesjTpy-j T-y- - - FTV to, V V Register sdZish - - "- JL- tJULliLJULLtLje SAOt output (.ii compare 4 Bbfxod element AND 5 L / Output multi-PAEK1 13ri 1. Block Outputs - Memory 3 L / yv figure 1