SU1709526A1 - Digital-to-analog converter with automatic correction of nonlinearity - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of precision digital-to-analog converter systems. The purpose of the invention is to improve the accuracy of the conversion. A digital-to-analog converter with automatic nonlinearity correction contains input buses 1–3, a shaper of 4 codes, a control output bus 5, a multiplexer 6, an analog-to-digital converter 7, a decoder 8, a reference voltage shaping unit 9, m additional multiplying bipolar pn mifroanalogovyh converters 11.111.t, adder. 12 and information output bus 13. The schemes of the main blocks 4, 6 and 9 are presented. A positive effect was achieved due to the introduction of the decoder 8, the block 9 of the formation of reference voltages and additional digital-analog converters 11. The increase in accuracy is due to the compensation of the transmission errors of the adder 12 while reducing the requirements to the accuracy of the components. 3 hp f-ly, 6 il 21-'n-mi ^ l] YuJ213

Description

The invention relates to electrical measuring equipment and can be used in the construction of precision digital-to-analog converters (DACs), as well as in various kinds of instrumentation, control systems and information transmission.

A digital-to-analog converter with automatic nonlinearity correction is known, containing a reference voltage source, first and second D / A converters, analog adder, comparator, switch, first and second registers, trigger, control unit, correction calculator, digital adder, and sensor of the code to be converted.

The disadvantage of this converter is the presence of a methodological error in determining the correction codes for the output voltage of the DAC. At the same time, the indicated error can reach several units of the lower bit of the first DAC. In addition, if the transform function of the first DAC has gaps greater than the low order unit, these faults cannot be compensated.

Also known is a digital-to-analog converter containing the first and second DAC, adder, AC amplifier, first and second comparators, first and second analogue measures, clock generator, register, random access memory (RAM), reversible counter, first and second elements And Zleme T AND DO NOT.

The disadvantage of this converter is the considerable time required to determine the correction codes.

The closest in technical essence to the invention is a DAC with automatic nonlinearity correction, containing the first and second DACs, adder, analog-to-digital converter, pulse amplitudes, -OZU, first and second registers, driver, synchronization unit, peri / iCTp shift, adder, multiplier and accumulator adder.

The functional circuitry of the DAC contains the first and second registers, the multiplexer, the block (correction calculations, the first DAC performed on a resistor binary coded divider and reference voltage source, the second DAC, analog adder, analog-to-digital pulse amplitude converter, RAM, driver codes, synchronization unit, input bus of the code being converted, input code input bus, converter operating mode control bus, bus

ready to receive in one code and output bus.

The first DAC is the main one. The second DAC is designed to compensate for errors introduced by the first DAC.

Since the first DAC is made on a resistor binary code-controlled divider (KUD), its error Au (h)

is described by the following expression; nI

AU (h) 2 (2-a, -2,) DKed |,

j 1

where ЕО is the output voltage of the source of the reference voltage; ai is the bit of a digit code, ai € {0; 1}; Aced - the error of the elementary divider of the i-ro bit of QCD.

Considering that A differential i A Cad | is fair

  Au (h) Eo (

aj) adif | -G

a |

j 1 2

 one

where dif1 K {2-) - K {2 - 1) 4- K (1) is the local differential nonlinearity of the 1-st bit of KUD;

K (.) Is the real division factors corresponding to the numerical values of the control code 2 -1.1. In the last expression, we replace the local differential nonlinearity of the f-ro bit of the QCD with the local differential non-linearity of the f-ro bit of the D / A converter:

Au (h) s (, -1: 21 :: 1z |) And “if ,.

  2

where is adif | Eo ADIF | U (2V- U () + U (1) 1 - local differential nonlinearity of the 1st bit of the DAC;

and (.) are the real values of the output voltage of the first DAC, corresponding to the numerical values of the control code 2 2 -1 and 1.

The D / A converter operates in two modes: Input Code Conversion and Differential Nonlinearity Definition.

In the Input Code Conversion mode, the control code is converted by the first DAC, the output of which is summed with the correction signal generated by the second DAC. At the same time, the code of the correction signal is calculated in each clock cycle of the digital-analog conversion using the correction calculation unit based on the functional dependence.

In the Definition of Differential Nonlinearities mode, using the analog-digital pulse amplitude converter, local differential nonlinearity codes of the higher bits of the first DAC are determined, which are entered into RAM and are used to calculate correction codes in the Conversion mode of the input code.

Obviously

UAi (h) -Ki (1-b (5 Ki) U (h) + K2 (1+ (5 K2) u, (h), where UAi (h) is the output voltage of the analog adder;

U (h) and Un (h) are the output voltages of the first and second DAC, respectively;

KI and Ka are the transfer coefficients of the analog adder over the first and second inputs, respectively;

b KI and dK.2 are the errors of the transmission coefficients for the first and second inputs of the analog adder, respectively.

Besides,

U. (h) Ml. (H).

Then the error of the output signal of the D / A converter can be written as follows: AUAc (h) K2-dK -Unth),

Therefore, a disadvantage of the known digital-to-analog converter is the occurrence of an error in the introduction of a correction signal caused by the error in the transmission coefficient of the analog adder on the second input.

The aim of the invention is to improve the accuracy of the conversion of the input code.

The goal is achieved by the fact that the converter contains a multiplexer, the first information inputs of which are connected to the corresponding outputs of the first group of outputs of the code generator, the first output of which is connected to the control input of the multiplexer, the outputs of which are connected to the corresponding information inputs of the main multiplying digital-analog converter, the output of which connected to the first input of the adder, the second input of which is connected to the output of the first additional multiplying bipol p The digital converter’s converter, the output of the adder, which is the output information bus, is connected to the information input of the analog-digital converter, the synchronization input of which is connected to the second output of the code generator, and the output of the result readiness is connected to the first input of the code generator, the second input of which is the mode control input bus and the third output is a control output bus, a decoder is entered, (t-1) additional multiplying bipolar digital-to-analog converters and b a unit for forming reference voltages, the corresponding outputs of which are connected to the inputs of the reference voltage m of additional multiplying bipolar digital-to-analog converters, the outputs of which, besides the first, are connected to the corresponding inputs of the adder, information

0 inputs m additional multiplying bipolar digital analog converters are connected to the corresponding outputs of the corresponding group of outputs of the decoder, the inputs of which are connected

5 to the corresponding outputs of the multiplexer, the second information inputs of which are the input code to be converted, the outputs of the second group of outputs of the code generator are middle with the corresponding synchronization inputs of the reference voltage generation block, the information inputs of which are connected to the corresponding information outputs of the analog-digital converter, and the reference input the voltage is combined with the input of the reference voltage of the main multiplying digital-to-analog converter and is the input bus of the reference th voltage.

0 FIG. 1 shows the block diagram of the proposed digital-to-analog converter (DAC) with automatic nonlinearity correction.

A DAC with automatic nonlinearity correction (Fig. 1) contains a bus 1 of an input analog signal, an input bus 2 of a convertible code, a bus. 3 control mode of the converter, shaper 4 codes, output bus 5 control, multiplexer 6, analog-digital block 7, decoder 8, block 9 of formation of reference voltages, basic multiplying digital-analog converter 10, additional multiplying bipolar

5 DAC 11, the input adder 12, the output bus 13 of the Converter.

The second group of information inputs of the multiplexer is connected to the input bus 2 of the converted code, the first input

0 shaper codes connected to the input bus 3 control mode of the converter, and the third output - with the output bus 5 control, the first input of the main multiplying DAC 10 is connected to the input bus 1 analog signal, the output of the adder 12 is connected to the output bus 13 of the converter and the second input analog-to-digital unit 7, the first input of which is connected to the fifth output, and the second output - to the second input of the form control panel 4

codes, the group of the first information outputs of which is connected to the first group of information inputs of the multiplexer, the group of information outputs of which is connected to the group of information inputs of the main multiplying DAC 10, the output of which is connected to the first input of the adder 12, the first input of the block 9 of the formation of the reference voltage is connected to the input BUS 1 analog signal, a group of second information inputs - with a group of fourth information-outputs shapers 4 codes, rpynrta third information inputs - with a group of first x information outputs of the analog-digital block 7, respectively, the corresponding outputs of the group of information outputs of the block 9 of the formation of reference voltages are connected to the first inputs of the corresponding additional multiplicative bipolar 1DAP 11, the outputs of which are connected to the corresponding inputs of the adder 12, and the group of the second information inputs from corresponding groups of information outputs of the decoder B, the group of information inputs of which are connected by a group of information outputs of multiplexer 6, the third input of which pogo connected to the second output of the coder 4 codes.

Fig. 2 is a functional block diagram of the formation of reference voltages, which contains m registers 22 and multiplying bipolar digital-to-analog converters 23,

FIG. 3 shows a functional diagram of an analog-digital unit 7 containing an amplifier 24 of an alternating signal, the first 25 and the second 26 analog measures, the first 27-1 and the second 27-2 comparators, the same two 28, the first 29-1 and the second 29-2 two-input AND elements, three-whorled element OR 30, reversible c "(etchik31.

FIG. 4 shows a functional diagram of a former 4 codes, containing the first 32-1 and second 32g2 one-shot, two-input element OR 33, generator 34, RS flip-flop 35, D-trigger 37, register 36, t-input element OR 39, rec & counter 40, () two-input element And 38-1,39-2 and 41-1, ..., 4T-t,

FIG. 5 shows a functional diagram of the decoder 8, containing m inverters 42.

As for the prototype, the error of the conversion function of the main multiplying DAC 10 is determined by the following expression:

Au (h) EO 5 (ai - 2 -r-aj) Ldif | , (1), 1 2

where ЕО is the input voltage on bus 1;

Adif (- differential nonlinearity of the 1st bit of the DAC.

The sum in parentheses is the numeric value i-1 of the lower regions of the control code {ai-i, ..., ai}. The plots of the dependencies (1) have the form shown in FIG. 6

From the analysis of these dependencies, it was concluded that each jump is determined by the differential nonlinearity of only one bit, and the jump from the 1st bit appears when changing the digit digits of the control code with (a {i 1; aj-1 0) on (О, - а -1 - 1) regardless of the state of bits, the numbers of which are greater than I.

We write the 1st term of the sum of expression (1) in the form. - :, | 1 ,. V

AU (h, UA ,, (&AIA.;.

It is easy to show that this dependence

it is easily formed using a two-multiply DAC, whose reference

 A IFPg is equal to Eo - .T, and the control code is defined by the following relations:.-Bi-ai, -v-v-;,; -. . .four

.

In this case, the output voltage of the DAC can be written as

itcAp (b) Eo Adif (| - | bj)

or

1 1-1 2

IcAp Yoo Adif e 2

Comparison of the right side of expressions (2) and (3) shows their complete identity. Thus, using the described two-pole multiplying DACs, one can compensate for the nonlinearity of the conversion function of the main DAC 10.

The proposed u-analogue converter with automatic nonlinearity correction works in two modes: Input code conversion and Differential nonlinearity determination. In Input Conversion Mode

code by a signal on bus 15 coming from the output of the 4 code generator to the control input of the multiplexer 6, the outputs of the latter are connected to bus 2 of the data of the code being converted. As a result, the control code from bus 2 is fed to the information inputs of the main DAC 10 and decoder 8. At the same time, a UCh signal is generated on the converter output bus 13) EoKK (h) + 5 KiUni (h), I n - m + 1 GDO K ( h) is the real conversion function of the main DAC 10; K (b) a, + AK (h); dk (s) AiSh; Uni (h) is the output voltage of the additional DAC 11; K and Ki are the transfer coefficients of the analog adder for each of the inputs. The analog inputs of the DAC 11 from the outputs 21 of the block 9 for the formation of the reference voltages receive voltages proportional to the differential nonlinearity of each 1st bit, i.e. Eo Adif |, and the corresponding information inputs of the DAC 11c outputs 20 of the decoder 8 receive the code combinations {aH, ai-i; ... ai}. As a result, the output signal of the converter on the bus 13, taking into account (3), (4), can be represented as:, -,., U (h) rEoKKfh) E: KiE „Л« p; K; (0; IГai jt : n-rn-f1 S-1 Z Ж Иrs ШЬ) - Е „К &, у„ Е „К01а, -Ь; 1 ;-) ,. Yeo | 4 4 ° -B "7 / YA it is obvious that, when performed equal to K -KiKii, the last term of expression (5) is compensated with a given accuracy. The number m of compensated high-order bits is determined by differential non-non-linear low-order bits of the DAC. In most cases, it is enough to choose t 6-8. When a single pulse arrives on the bus 3 controlling the operating mode of the converter, the converter is switched to the Definition of Differential Nonlinearities mode. In this case, a single signal on the bus 15c of the output of the former 4 codes, the outputs of the multiplexer 6 are connected to the bus 14. At the same time, the code combination 00 ... 01 is entered into the shift register 36. The presence of at least one unit at the outputs of the shift register 36 transfers the latter by a signal from the output of the element OR 39 to the information shift mode. In addition, a pulse generator 34 is started with a single signal on the bus .15. As a result, at the outputs 14 of the counter 40, a series of adjacent codes h oi {an-m + i 1; aj-i O} h-100 {aj i 0; aj i 1}. At the same time, an alternating square-wave signal is generated on the output bus 13 of the converter, the amplitude of which carries information about the differential nonlinearity of the (n-m + 1) -th bit. The amplitude of the variable signal can be represented as Unc UAi (h) - UAi (h-l) ЕоК K (h) -K (h-1) + (h) -Uni {h-1). l n-m4-1 From (1) it follows that when changing the adjacent codes h and h-1 KI Uni (h) - Uni (h-l) «0. I n -m 4-2 Therefore. Unc Eo to (r + Ldif |) + KI (Uni (h) - Uni (h - 1); 11) HELP of the analog-digital block 7, the amplitude Unc of the alternating signal is compared with the output signals of analog measures 25 and 26, the nominal values of whose output signals equal, respectively: Ui Kv (Eo - A): U2 Ky (Eo A), where A is the permissible deviation of the real unit of the least significant bit from the nominal one. Depending on the comparison result, the comparators 27-1 and 27-2 produce signals by which pulses from the output of the one-shot 28, the code 19 of the counter 31 is increased or decreased by one and a pulse on the bus 16- (pt + 1) h anosit to the 22-t register. With the help of an additional two-pole multiplying DAC, the 23-t is converted into an analog signal EoKi (nm - (- i). which is an input signal of the 11-t dual-polar multiplying DAC, which compensates for the differential nonlinearity {n -t + 1) -th bit of the main DAC 10. The next mode of operation of the analog-digit {power unit 7, DAC 23-m and 11m will continue until the inequality Ul KyUnc U2 is satisfied. (6) where Q is the gain of the variable signal amplifier 24. In this case, the condition Eo K Adif (n-m + 1) -K (nmH) Un (nmH) (h) Un (n-m + 1) (h-1) or taking into account (4) and (5) To "-KiKii,

which makes it possible to compensate for the differential nonlinearity of the (n-m + 1) -ro bit.

When the inequality b is fulfilled, the analog-digital unit generates a pulse on the bus 18, according to which information is shifted in the shift register 36. At the outputs of the shift register 36, the combination code 00 ... 010 is set, the further t-1 clock cycles of the converter in this mode are similar to the first clock cycle.

At the end of the t-th cycle, with the arrival of a single impulse, the code combination 0 ... 0 is set at the outputs 36 of the latter via bus 18 to the shift register 36. As a result, at the output of the element OR 39, a zero signal is set, which translates the shift register 36 into the information entry mode. At the same time, the output signal of the single-selector 32-2 RS-Tpt rrep 35 is switched to the zero state, and the output signal of the RS flip-flop 35 is fed to the upstream control bus 5. In this case, the converter is transferred to the Input Code Conversion mode.

Thus, in comparison with the prototype, the proposed device achieves an increase in the accuracy of the digital-analog conversion by compensating for the errors of the transmission coefficients of the analog cyf-sp rropa while reducing the accuracy requirements of the components. ,

The main DAC 10 (Fig. 2) is made on the 572PA2 chip, the additional DAC 11 (Fig. 2) and DAC 23 (Fig, 3) of the unit 9 for the formation of reference voltages are made on K572Pa1G, the shaper 4 codes, analog-digital unit 7, the decoder 8, the block 9 of the formation of the reference voltages (FIG. 2) is performed on the microcircuits K544UD1, K521 SAZ and microcircuits of the series K561. . The T-application of K-bit additional D / A converters 11 and 24 provides for an increase in linearity of the iifro-analog conversion by a time while observing the principle of superposition in the main DAC 10. If the superposition principle is in the main DAC, the linearity of the conversion is limited to non-superpositional errors and is 0.001%.

Claims (4)

Claim 1. Digital-analogue converter with automatic nonlinearity correction, containing a multiplexer, the first informational inputs of which are connected to the corresponding outputs of the first group of outputs of the code generator, the first output of which is connected to the control input of the multiplexer, the outputs of which connected to the corresponding information inputs of the main multiplying digital-to-analog converter, the output of which is connected to the first input an adder, the second input of which is connected to the output of the first additional multiplying bipolar digital-to-analog converter, the output of the adder, which is the output data bus, is connected 0 with the information input of the analog-digital converter, the synchronization input of which is connected to the second output of the formatting code, and the output of the readiness of the result is connected to the first input 5 of the code generator, the second input of which is the mode control input bus, and the third output - control output bus, characterized in that, in order to increase the conversion accuracy, a decoder is entered into it, t-1 additional multiplying bipolar analog converters and a shaping unit reference voltages, the corresponding outputs of which are connected to 5. the reference voltage inputs of the corresponding m additional multiplying bipolar digital-to-analog converters, the outputs of which, except the first, are connected to the corresponding inputs of the third (t +) - adder, information inputs m additionally 1x multiplying bipolar digital-analog converters are connected to the corresponding group of outputs decoder whose inputs 5 are connected to the corresponding outputs of the multiplexer, the second information inputs of which are the input bus of the code being converted, the outputs of the second group of outputs of the code generator are connected to the corresponding synchronization inputs of the reference voltage generation unit, the information inputs of which are connected to the corresponding information outputs of the analog-digital converter, and the input the reference voltage is combined with the input of the reference voltage of the main multiplying digital-to-analog converter and is the input oh the reference rail, 0 2. The converter according to claim 1, 1, and TL is also the fact that the block for forming reference voltages is made in the form of m registers and m is multiplied (their bipolar digital-to-analog converters, the outputs of which are the corresponding outputs of the block, and the information inputs are connected to the corresponding outputs of the corresponding register, the synchronization inputs of which are corresponding to the synchronization inputs of the block. the information inputs of the first register are combined with the corresponding information inputs of the remaining t-1 registers and are the corresponding information inputs of the block, the input voltage of the first multiplying bipolar digital-to-analog converter is combined with the inputs of the reference voltage of the remaining t-1 multiplying bipolar digital-analogue converters The input is a reference voltage. 3. The converter according to claim 1, of which is that the analog-to-digital converter is made in the form of an amplifier of an alternating signal, the first and second analogue measures, the first and second comparators, the first, second and third elements And , a reversible pulse counter and a one-shot, the input of which is the synchronization input of the analog-to-digital converter, and the output connected to the first inputs of the first and second elements And with the non-inverting input of the third element And, the output of which is the output of readiness of the result of the analog-digital converter, and the first and second inverting inputs are combined with the second inputs of the first and second elements of the first and second comparators respectively, the first the inputs of which are connected to the outputs of the first and second analogue measures, respectively, and the second input1d are connected to the output of the alternating circuit, whose input. is the information input of the analog-digital converter, the outputs of the first and second elements of AND are connected respectively to the input of the summation and subtraction of a reversible counter and pulses. The outputs of which are information outputs of the analog-to-digital converter. 4. Converter according to. Section 1, of which is that the driver of the codes is made in the form of the first and second one-shot, RS- and D-flip-flops. the first and second OR elements, pulse generator, shift register, t + 2 AND elements and reversible pulse counter, the outputs of which are the first group of outputs of the code generator, and the information inputs are combined with the corresponding inputs of the first OR element, with the first inputs of the corresponding first m And elements and connected to the corresponding outputs of the shift register, the control input of which is combined with the input of the first one-shot and connected to the output of the first OR element, and the synchronization input is combined with the S input D-t the trigger and connected to the output of the second OR element, the first input of which is the first input of the code generator, and the second input is combined with the S input of the RS flip-flop, the R input of which is connected to the output of the first one-vibrator; the inverse output is the third output of the code generator, and the direct output is the first output of the code generator and is connected to the input of the pulse generator gating, the output of which is connected to the first inputs of the (t + 1) -th and (t + 2) -gb elements And, and to the synchronization input of the D-flip-flop, inverse output which is connected to its D-in and the second input (t + 1) of the I item, and the direct output with the second input (t + 2} of the I item, the output of which is the second one) by the code generator and connected to the write enable input of the reverse information pulse counter, the subtracting input of which is combined with the SECOND inputs of the first m AND elements and connected to the output of (t + 1) -th element AND, the input of the second single-oscillator is the second input of the code generator, and the output is connected to the second input of the second element OR, the serial input entering shift register information combined with passages except the first parallel data input shift register connected to the bus and a logic-zero, first ; the input of the parallel input of the shift register information is connected to the bus of the logical unit; the outputs m of the first And elements are the second group of outputs of the code generator. Win-m l} Fig5