SU1179533A1 - Analog-to-digital converter - Google Patents

Abstract

1. ANALOG-DIGITAL CONVERTER containing a comparison unit, a control unit, a first register, a digital-analog conversion unit whose output is connected to the first input of the comparison unit, the second input of which is the input bus of the device, and the output connected to the first input of the control unit, the second input which is connected to the startup bus, and the first output buses are connected to the corresponding inputs of the first register, the outputs of which are the output buses of the device, characterized in that, in order to improve speed, it contains the block of elements OR, the second register, a permanent storage device, the outputs of which are connected to the corresponding information inputs of the second register, the control inputs of which are connected to the corresponding second output buses of the control unit. and the outputs to the corresponding first inputs of the OR block, the outputs of which are connected to the corresponding inputs of the D / A converter unit, and the other inputs to the corresponding outputs of the first one. register. 2. The converter according to claim 1, about t and h with the fact that the control unit is executed on the clock pulse generator, n RS-flip-flops, shift register, (n + 1) elements I, the first inputs n of which are combined and are the first input of the control unit, the second inputs are connected to the corresponding AND outputs of the register (L shift, the code of the first I element is connected to the R input of the first RS flip-flop, and the outputs (n-1) of the I elements to the corresponding first R- the inputs of the corresponding (p-1) RS-flip-flops, the second R-inputs of which, the first input of the shift register and the S-input of the first t igger are combined and are the second input of the control unit, S-BXO dy (n-1) RS-flip-flops are connected to; on the joint venture the corresponding outputs of the shift register, the outputs n of the RS-flip-flops are with the first output buses of control unit 00, with Thereby (n + 1), the shift register code is connected to the inverted input of the And element, whose direct input is connected to the output of the clock generator, and the output to the second input of the shift register, whose first output and output (n + 1) of the And element are output control unit tires.

Description

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The invention relates to computing and digital measurement technology and can be used to convert analog values to digital ones.

The purpose of the invention is to increase the speed of the analog-digital converter.

 The drawing shows a structural diagram of the analog-to-digital converter.

The analog-to-digital converter contains an input bus 1, a comparison block 2, a digital-analog conversion block 3, a first register 4, a control block 5, a second register 6, an OR block 7, a read only memory 8, and output buses 9.

The output of block 3 is connected to the first input of block 2, the second input of which is the input bus 1 of the converter, and the output is connected to the first input of control unit 5, the second input of which is connected to the start bus, the first output buses are connected to the corresponding inputs of the first register 4, and the second output buses of block 5 are connected to the control inputs of the second register 6 whose information inputs are connected to the corresponding outputs of the persistent storage device 8, and the outputs to the corresponding first - inputs of the block 7, cat outputs cerned are connected to respective inputs of unit 3, and the second input - to the corresponding outputs of the first register 4 which are output devices tires.

The control unit 5 contains n RStriggers 10, - 10 |, (n + 1) AND 11, - 11p, j shift register 12 and generator 13 clock pulses.

Block 3 of the digital-analog conversion (DAL) should be built on the basis of redundant measuring codes, which include Fibonacci p-codes, golden p-proportion codes, as well as generalized Fibonacci codes,

For analog-to-digital converters containing a DAC feedback circuit, built on the basis of redundant measurement codes, the occurrence of coding errors such as incorrect discharge switching off does not cause unbalance

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input signal A compensating signal A |.

In order to exclude, when analog-to-digital conversion, type coding errors. Incorrect switching on of the discharge, in the process of balancing Agji with the signal A, an asymmetry is introduced, which is that at each -th bit of a coded coding simultaneously with the t-th bit of weight Qn include in the general case a group of some lower-order bits with a total weight The value of ldd is determined by the formula:

Aq.

Doping 2 Based on the values of AQ.Q, the code K, the lower bits, is synthesized, which, when the device is manufactured, is entered into the permanent storage device 8. If the ratio between the weight of the bits of the code used is a constant number, then

, forming in the process of balancing on each subsequent j-th cycle of the code combination K; dd, the source code combination is shifted, Kg by one bit to the right. The joint inclusion of the f-ro and a group of some of the lower-order bits causes the actual weight of the G-th digit to increase. At the same time, if the difference uAAc at the end of the preceding equilibration cycle is close to the value of the f-ro bit, then in the current cycle the comparison unit generates a logical signal causing the -th bit to turn off, and - further equilibration is carried out by bits with numbers less than f. Thus, the coding type errors are incorrect. Inclusion of the bit

5 When converting an input analog value into an analog-to-digital converter code containing a DAC, built on the basis of a non-redundant binary code, such an asymmetry of the balancing process is fundamentally impossible. In this case, the error of the type coding causes the input analog to turn off

5 A value „cannot balance

signal A c up to the youngest bit of the DAC. Therefore, the result of the conversion of the digital equivalent of KV is incorrect. If an analog-to-digital converter is implemented on the basis of a redundant measuring code, it becomes possible to perform the correct analog-to-digital conversion with type-coding errors. Incorrect switching off of bits. The introduction of asymmetry in the balancing process eliminates the type encoding errors. Incorrect inclusion of the discharge. These circumstances make it possible to significantly reduce the time of each j-ro clock of the bit-coded coding. At the same time, there is no need to carry out an exact, for example up to half of the lower order bit, for each balancing step, and to compensate for the input Aru; analog signals 4 It is enough to allocate the time necessary for establishing transient processes in the DAC and the comparison unit with the error SQ for one step of a bit balancing. The value of SQ depends on the redundancy of the code on the basis of which the DAC is built, and is determined by the formula: 8Q 2о: - 1, where M. is the ratio between neighboring members of the code on the basis of which the DAC is built. For the Fibonacci number with p 1, for example, (0.61803, o.), The error So is 0 23.6%. The device works as follows. At the first step of converting the input analog value A to the code K, the most significant bit of the first register 4 is set to one by the signal of the control unit 15, and the Cdop code combination is recorded in the second register 6 from the permanent memory 8, through block 7 The elements of the IL code combinations K and from the outputs of the first and second registers respectively arrive at the input of block 3, at the output of which appears a compensating analog signal Ak, (Qn-, - Рссg ,,). where Q h is the weight of the most significant bit of block 3. Comparison of the compensating signal A | and the input analog signal Agjj is performed using comparison block 2, with the output signal Y: of this block subject to the following relation: fo. if A p A j if A А A, M KJ At the same time, if on the first step of balancing Y O, the first bit of the first register A is set to the zero state, if Y 1, then it remains in the unit state. In the second analog-digital conversion cycle, the signal from control unit 5 controls the contents of the second register 6 to shift one bit to the right, with the result that the output of the register 6 is the Kdovz code combination. The next highest digit in the first register appears at the same time. 4. At the same time, a compensating signal A appears at the output of block 3 of the DAC. As a result of comparing the input Aj and compensating A, the analog signals of this bit are either set to zero (Yj 0) or remain in one ary state (Y 1). The device on any j-th cycle works similarly. The operation of the device ends in (n + 1) -th cycle of bit-coded coding. At the same time, the input analog signal A gj (balanced by compensating 1 ™ signal from block 3 of DAC A. with an accuracy of one of the lower (zero) bit of block 3 of the DAC and on output bus 9 appears a code equivalent to the analog signal Agj. When implementing DACs based on redundant measurement codes it is possible to increase the speed of the analog-digital converter despite the increase in the number of conversion cycles caused by the increase in the number of bits for the redundant measurement code . In comparison with the binary code Factor Yf increase in speed in the general case is defined by the formula: where TH t - duration of the cycle of the binary coding bit-wise ASCHTS t- - stroke length coding bit-wise ADC

built on the basis of redundant codes;

Y is the coefficient of elongation of the discharge grid. PL 6 I 7 I I 9 b 1 T 82.51 2.82 3.133.46. 3.78 4.11

where n is the number of bits of the binary DAC. The dependence of y y st n at o4

About 1.618 ... shown in the table.

16 Moreover, (Пг «2 En 2 I If 8 en 2oi - l42- № 2-1 2 / e oitq 5 1 I 4,44 4,78 5,11 5,44 5,77

Claims (2)

1. ANALOG-DIGITAL CONVERTER, comprising a comparison unit, a control unit, a first register, a digital-to-analog conversion unit, the output of which is connected to the first input of the comparison unit, the second input of which is the input bus of the device, and the output is connected to the first input of the control unit, the second input of which connected to the trigger bus, and the first output buses are connected to the corresponding inputs of the first register, the outputs of which are the output buses of the device, so that, from the action, in cops OR, the target is different I Bystroň administered block elevtoroy register his constant storage device, outputs of which are connected to respective data inputs of a second. register, the control inputs of which are connected to the corresponding second output buses of the control unit, and the outputs to the corresponding first inputs of the OR block, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter unit, and other inputs to the corresponding outputs of the first register. 2. The converter according to π. 1, characterized in that the control unit is made on a clock, η RS-flip-flops, shift register, (n + 1) AND elements, the first inputs η of which are combined and are the first input of the control unit, the second inputs are connected to the corresponding AND the outputs of the shift register, the output of the first AND element is connected to the R-input of the first RS-trigger, and the outputs (n-1) of the And elements are connected to the corresponding first R-inputs of the corresponding (n-1) RS-triggers, the second R-inputs of which, the first input of the shift register and the S-input of the first trigger are combined and are the second the control unit, S-inputs (p-1) of the RS-flip-flops are connected to the corresponding outputs of the shift register, the outputs η of the RS-flip-flops are the first output buses of the control unit, while (p + 1) the output of the shift register is connected to the inverse input of the And element the direct input of which is connected to the output of the clock generator, and the output m (0 SP with it 00 to the second input of the shift register, the first output of which and the output (n + 1) of the element And are the second output buses of the control unit.