SU388361A1 - FUNCTIONAL CONVERTER ANALOG — DIGIT - Google Patents

Description

one

The invention can be used in combined computing complexes combining analog and digital equipment.

Typically, information transmitted from the analog part to the digital part is converted according to some functional dependency. This conversion can be performed in both analog and digital form. Conversion to analog form requires the presence of a universal diode functional driver. The function obtained at the output of the converter in the form of a varying voltage is converted using an analog-digital converter into a digital form.

Such functional converters are difficult to set up, costly equipment and do not provide sufficient accuracy. In addition, they do not allow automatic tuning to a given function. Therefore, functional conversion in analog form is unacceptable in most cases.

In digital function conversion, the analog argument of a given function is first converted using a digital-to-digital converter using an analog-to-digital converter. Then, a functional transformation is performed either by using appropriate programs in digital computing facilities, or by using some set of decision blocks in digital integrating machines, or, finally, by setting 5 functional dependency tables in the case where the analog representation of the function is absent or too complex.

However the conversion is in digital form

0 requires a lot of time when calculating functions on digital computers and a large number of decision blocks in digital integrating maschines.

The purpose of the invention is to reduce costs.

5 equipment and time to calculate the functions of the analog argument.

In the proposed analog-to-digital functional converter, this goal is achieved by using a memory device in it to store information about the slope of the linear segments of the piecewise linear curve approximating the original function and the simplest linear converter. In this case, the outputs of the higher bits of the counter are connected to the address buses of the memory device, and the outputs of the lower bits of the counter and bits of the register of the number of the memory device are connected to the inputs of the linear converter, the output of which

0, the function is incremented. The block diagram of the proposed functional analog-to-digital converter is shown in FIG. one; in fig. Figure 2 shows stepped curves, approximating linear, for four values of the slope and corresponding to these values of the sequence of increments of the function Ar / depending on the state of the counter. The analog-to-digit functional converter includes counter 1, the analog-to-digital converter 2, the comparison circuit 3 and the AND 4 circuit. The counter / (high bits) is used in the functional converter as a memory address counter 5. The counter outputs The (and junior bits) and the register of the number of the memory device 5 are connected to the inputs of the linear converter 6, the output of which forms elementary (unit) increments of the function in potential form. In the functional converter, a piecewise linear approximation of a given function and a step approximation of linear segments are applied. The argument x of the function y is divided into 2 ™ segments, each of which 25 contains 2 elementary increments of A /; t is the number of high bits, n is the number of low bits of the counter /. The values of m and, as well as the ratio between them, are chosen from the conditions of allowable majesty of 30 errors of linear and step approximations. Then the function is scaled so that the greatest amount of slope is less than one. In this case, the possible slopes are equal to ± - (r 0,) and are stored in a memory device, and the slope of the approximation is stored in the cell with this address. The parameter is rhvHr., HH n disp.,. Р "pmrp, .ppt-40 th function on the segment, the number of which is equal to this address. In the initial state in the counter Y, the initial value of the analog argument X is found, in the memory number register, the device is the 5 initial value of the slope 5 of the approximated function. The sign of the slope from the digit of the sign of the number register is displayed on the bar “sign Ay of the sign of the increments of the function. In the senior bits of the counter / the number of the segment being processed is found, in the lower 0 bits of the counter there is the increment number Ax on the given segment. If we designate, starting with the lower order bits, the unit states of the register bits, the numbers in the storage device 5 through r, 55 (i, 2, ..., p), and the counter / through s, (, 2, .. ., A), then the operation of the linear converter 6 can be described by the logical formula I Ar / f-5d5 „1 5„ „2 ... S -ir Sn-iSn-2 ... 5; -f 60 + ... + rn-iS, S, + r „5„ () where Ay is the increment module of the function y, which can take one of two values, “O or“ 1. 5 20 35 65 When the input analog value l is changed; which goes to one input of the comparison circuit 3, the output of the latter has a error signal equal to "1 if the output value of the converter 2 digit-analog differs from the input. The output signal from the comparison circuit opens the AND 4 circuit, and the increment pulse D of the independent variable, applied to the second input of the AND 4 circuit, passes to the input of the counter / - the counter state changes, and the output values of the converter 2 and linear Converter 6. Output | Ar / | The linear transducer 6 has a code corresponding to the increment value of the function on the given segment when newly formed in the counter / increment number Ax. At the output of circuit 3, the code "1 is maintained until the output value of the 2-digit-analog converter does not compare with the analog input value x. In this case, the pulses A / come from the counter /. As soon as the lower bits of counter 1 overflow, the overflow pulse arrives at the high bits of the counter. The state of the counter / is changed by one. This prepares the next cell with a new slope value for reading from a memory device. The overflow pulse from meter 1 is also applied to the reading memory of the memory device. In the register of the number of the memory device 5, respectively, a new value of the slope of the linear segment of the approximated function is read. An example of the linear converter 6 at. In this case, the register number of the storage device 5 has four numeric bits and one digit, the counter / also contains four bits. I will give - - “- g-- --- g-. -. . the register corresponds to the following slopes: the first bit Vie, the second / le, the third Vie and the fourth / i6 (in Figs. 2a-2d, respectively). The increment Ar / is equal to the unit prir ........ t - --... „. J,.,.„. A / dl tilt equal to Via, then, when the contents of the counter is eight, to tilt Vie, - when the contents of the counter are four and twelve, and t, e. The slopes shown in FIG. 2 are major. The remaining slopes are formed by summing the main ones, and the arithmetic summation coincides with the logical one. As a result, it was possible to realize the slopes with the help of the “AND schemes, and their summation with the help of the OR scheme. the formula () each addend forms "№" of the main slopes. Which of the slopes must be formed is determined by the bits of the number register. So, if in the first digit fi of the number register there is one, then the slope is Vie; if the units are contained in all bits, then all major slopes are formed. The sum of these slopes gives the slope, the value of which is in the register number of the storage device 5. This is

slope ° / i6, which is equal to the sum of the slopes "/, 6 and Vi6 (Fig. 2e).

Setting up the converter for a given function is quite simple by writing the slope values to a memory device.

In order to build a functional converter, a simple storage device and a linear converter are required. So, for a twelve-bit converter, an analog is a digit, it is enough to have a memory device of 128 six-digit numbers. To implement a linear converter, it is necessary to have only five AND patterns and one OR circuit.

The reduction in the time for computing functions is obvious, since the actual process of calculations is missing. The formation of function increments occurs almost simultaneously with the conversion of the analog argument to a digital code.

Subject invention

A functional analog-to-digit converter containing a counter, characterized in that, in order to simplify and increase the speed of the converter, it contains a digital-analog converter, linear

the converter, the comparison circuit, the AND circuit and the storage device, the outputs of the higher bits of the counter are connected to the digital-analog converter and through the memory device to the linear converter, the low-level outputs of the counter are connected to the linear converter and the digital-analog converter, the output of which comparison circuit and circuit "And connected to the meter.

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