SU1665547A1 - Variable tv signal delay line - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to improve the accuracy and expansion of functionality. The adjustable delay line / RLS / television signal contains a 3 clock generator, a driver of 2 clock pulses, a device with a charge coupling 1 / CCD /. The goal is achieved by the introduction of a block of 4 AND elements, a synchronized transducer 5 of the code in the time interval. Changing the information at the inputs of the parallel recording of the counter of converter 5 allows changing the delay time of the television signal from 0 to 12 µs. The converter 5 controls the operation of the CCD 1, the CCD 6 and the switch 9 in accordance with the transmission pattern. If an additional delay is required equal to the length of the CCD 6, then the mode of extrusion of extra information from the CCD 6 is excluded.

Description

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Transducer 5 allows changing the delay of the television signal within 0–12 µs. The converter 5 controls the operation of the CCD 1, the CCD 6 and the switch 9 in accordance with the transmission pattern. If additional delay is required

equal to the length of the CCD 6, then it turns off the mode of extrusion of extra information from the CCD 6. If there is no need for additional adjustment, then the CCD 6 clocking pulses are not supplied, and the switch 9 works only from the CCD 1. 3 Cp. f-ly, 5 silt

The invention relates to television and can be used in television receivers as part of VLSI analog signal processing with digital control.

The purpose of the invention is to improve the accuracy and expansion of functionality,

Figure 1 and 2 presents the structural electrical circuits of the adjustable delay line of the television signal; on fig.Z and 4 - structural electrical diagrams of the synchronized code converter in the time interval; Fig. 5 is a flow chart.

The adjustable delay line of the television signal (Fig. 1) contains a device 1 with charge coupling (CCD), a shaper of 2 clocks, a generator of 3 clocks, a block of 4 And elements, a synchronized transducer 5 of the code in the time interval.

Adjustable delay line of the television signal (figure 2) contains the first CCD 1, the first driver 2 clock pulses, the generator 3 clocks, the first block 4 elements And synchronized transducer 5 code in the time interval, the second CCD b, the second driver 7 clock pulses, the second block 8 elements AND, switch 9.

Synchronized Converter 5 code in the time interval (fig.Z) contains the first trigger 10, the second trigger 11, the first 12 and the second 13 elements AND - NOT, the counter 14,

The synchronized code converter 5 in the time interval (Fig. 4) contains a counter 15, a multiplexer 16, a memory block 17, a single pulse shaper 18, a register 19.

Adjustable delay line (Fig.1 and 3) works as follows

The 3 clock generator generates at the output two sequences of clock pulses arriving at the first input of the synchronized converter 5 of the code in the time interval and the input of the 4 element I. The clock signal arrives at the first input of the first trigger 10. The second input of the trigger 10 is pulsed, duration and position which correspond to the synchronization pulse of the input television signal. After the arrival of the synchronizing pulse, the trigger 10 is set to the Log.1 state on the trailing edge of the clock pulse. The signal Q from the output of the trigger 10 enters the second trigger 11, setting it to the state Log.0. At the output of the first element 1/1 - NOT 12 a pulse of information loading into the counter 14 is formed. The second element AND - NOT 13 starts to send counting pulses to the counter 14. Thus, the counter 14 is loaded into the state that determines how long the information in the CCD 1 needs to be delayed. The output of the trigger 11 prohibits the passage of a sequence of such pulses on the CCD 1 through the block 4 of the elements AND and the driver 2 of the clock pulses.

After passing the set number of pulses (when the counter reaches 14, the state Lor.000 ... O at the output of the loan of the counter 14 appears to be a pulse, which returns the trigger 11 to the state that allows further passage through the block 4 of the elements AND of the sequence of clock pulses on the CCD 1 and at the same time prohibits the passage of counting pulses to the counter 14. When the next clock pulse arrives, everything repeats from the beginning. Thus, the information on the parallel recording inputs of counter 14 can change the duration of the television delay Igna within 0-12 ms.

Adjustable delay line (figure 2 and 4} works as follows.

The 3 clock generator produces the clock pulses necessary for the operation of the CCD 1 and 6, as well as for the operation of the synchronized converter 5 of the code in the time interval. The synchronized code converter 5 in the time interval controls the operation of the CCD 1 and 6 and the switch 9 in accordance with the information flow diagram (Fig. 5). The flow of information is divided into time intervals (A, B, C, D ...). The diagram corresponds to the beginnings of these time intervals. The physical implementation of a CCD 6 on a chip is a delay line with one input and one output and has a certain length.

Due to the fact that it is necessary to obtain different delay times with its help, consider the general case of device operation, i.e. the length of the CCD 6 is chosen equal to the maximum required additional delay in the device, and the additional delay required in the device is shorter than the actual length of the CCD 6. Consider the mode (Fig. 5 a). The clock pulses are transmitted to the CCD 1 (they are not passed to the CCD), the switch 9 transmits information AL to the output. At the same time, information A2 is recorded at the input of the CCD 1. The CCD 6 stores the necessary information Bi and unnecessary information SG.

Then the clock pulses (fig. 5b) pass only to the CCD b (the CCD 1 stands), the switch 9 transmits information Bi to the output, and the information Br, which is lost by the CCD 1, is simultaneously recorded on the CCD. After reading the information Bi, the clock pulses ( Fig. 5b) is also supplied to the CCD 1, the switch 9 transmits the information Ci from the CCD 1. From the CCD 6, extra information Ci1 is pushed out, the necessary information is put in the right place. B2 (Fig.bg). At the same time, at the input of the CCD 6, the excess Ca information is recorded (fig.5d). Further, read-write occurs only from the CCD 1 until it is again necessary to transfer the missing & CCD 1 information Ba (fig.be). Then everything repeats again.

If an additional delay is needed equal to the length of the CCD 6, then the mode of extrusion of extra information from the CCD 6 is excluded. If there is no need for additional adjustment, then the CCD 6 will not be clocked, and the switch 9 only works from the CCD 1.

The synchronizable code converter 5 in the time interval (FIG. 4) generates control signals as follows.

Counter 15 operates in a cyclical mode, the cycle time in which is equal to the total time in the CCD 1 and the required additional delay time in the CCD 6. The output of the counter 15 through the multiplexer 16 determines the address in the memory block 17. The output of memory block 17 controls the operation of blocks 4 and 8 of the AND elements, as well as of the switch 9 in accordance with the indicated algorithm. A single pulse shaper 18 generates a single pulse on the leading edge of a television clock

Claims (4)

the signal by which the counter 15 is reset to the zero state. The first clock pulse then loads the counter 15 into the state determined by the information of the register 19. In the register 0 19 and the memory block 17, information can be changed (if necessary). At the same time, the address in the memory block 17 is established via the multiplexer 16 from the external control. Claim 1. Adjustable delay line of a television signal, comprising a clock generator, a clock pulse generator, the outputs of which are connected to the first inputs of the device with a wired connection, the second input of which is an input of the adjustable delay line of the television signal, characterized by In order to improve accuracy, the block of elements I and the synchronized code converter are entered into it in the time interval, the first input of which is connected to the first output of the clock generator, the second and third inputs of The second and third inputs of the adjustable delay line of the television signal are respectively, and the output is connected to the first input of the AND block, the second inputs of which are connected to the second outputs of the clock generator, and the outputs are connected to the inputs of the clock pulse generator, em with the output of the adjustable delay line of the television signal. 2. Delay lines of 1 each, so that the synchronized code-to-time code converter contains the first and second triggers connected in series, the first AND element — NOT and the counter, the output of which is connected to the second input the second trigger, the third input of which is connected to the Log.0 level, and the second output - to the first input of the second element AND - NOT, the output of which is connected to the second input of the counter, the third input of which is the third input of the synchronized code converter in the time interval, output and second in the stroke of which is connected respectively to the first output of the second trigger and the second input of the first trigger, the second output of which is connected to the second input of the first AND element, and the first input is connected to the second input of the second AND element and the first input of the synchronized code converter in the time interval. 3. The delay line pop.1, which differs from the fact that, in order to expand the functional possibilities, a second device with a charge connection was introduced into it, the second input of which is the first input of the adjustable delay line of the television signal, the switch and the second unit of series I and the second clock pulse generator, the outputs of which are connected by t first inputs of the second device with charge coupling, the output of which is connected to the second input of the switch , the first input of which is connected to the output of the first device with a charge coupling, and the third input is connected to the second output of the synchronized code converter in the time interval by the first input of the second th clocks element unit, wherein the switch is output to the second output ET adjustable delay line of the television signal. 4. The delay line according to Sec. 3, characterized in that the synchronized code converter in the time interval contains Lx1 W.H. holds the counter, a single pulse shaper, a multiplexer, a register and a memory block, the first input of which is connected to the third input of a synchronized code converter in the time interval, the first input of the multiplexer and the register input, the output of which is connected to the first input of the counter, the second input of which is through a single shaper the pulse is connected to the second input of the synchronized code converter in the time interval, the first input of which is connected to the third input of the counter, the first output and the fourth input of the cat cerned together, and the second output via a second multiplexer input connected to the second input of the memory unit, the first and second outputs which are respectively the first and second outputs of the code converter synchronizes the time interval. Out I 2 I 3 In 2 Q 8ti YU Q 13 7 /  ft Bx3 Output 1 Bi / x.2 Fay 0  h MI I | I I fli I c, eight c  PM C2 U | M, I / / I D; | C; I I Cr | 8g D  ; ; - | M I I 2 I / iГ ° I: SHZN u, 5 D  ;