SU1387182A1 - Programmed multichannel timer - Google Patents

Abstract

The invention relates to the field of radio electronics and can be used in devices for processing discrete information. The purpose of the invention is to improve the accuracy of formation of small time intervals between output pulses. The timer contains a discrete delay line 1, a memory 2, a control counter 3, AND 4.1, ..., 4 (N + 3) elements, 5.1, ..., 5.N triggers and an OR 6 element. The introduction of discrete delay line 7 , the switch 8 codes and the formation of new functional connections reduces the recovery time of the timer. 2 Il.

Description

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The invention relates to electronics and can be used in devices for processing discrete information, measurement technology, synchronizers.

The purpose of the invention is to improve the accuracy of forming small time intervals between output pulses by reducing the recovery time of the programmable multi-channel timer.

FIG. 1 shows the scheme of the proposed timer; in fig. 2 - time diagrams of the timer operation for the number of timer outputs equal to two (where te is the timer recovery time; tc is the control counter delay; 1u is the memory delay).

The programmable multichannel timer contains the first discrete delay line 1 (LLL), memory 2, control counter 3 (CS), logic gates 4.1-4. (N - (- 3), triggers 5.1-5.N, logical element OR 6, second discrete delay line 7, switch 8 codes.

The first input of the logic element OR 6 is connected to the input bus of the start pulse (FROM), the second input is connected to the output (M4-3) of the 4th logical element 4. (N4-3), and the output - to the input of the initial installation of the first discrete line 1 delays and the counting input of the control counter 3, the setup input to the initial state of which is connected to the output of the (N + 2) -ro logic element AND 4. (N + 2), and the outputs of the control counter 3 are connected to the first group of address inputs of the storage device 2 , the second group of address inputs of which is connected to the control input bus, the first The group of outputs is connected to the information inputs of the first discrete delay line 1, and the second group of outputs is connected to the first inputs of logic gates AND 4.1-4. (N + 3), the second inputs (N + l) -ro and (N + 2) -ro of the logical elements AND 4. (N + 1) and 4. (N + 2) are connected to the output of the first discrete delay line 1, the outputs of the logical elements AND 4.1-4.N are connected to the corresponding 1-inputs of the trigger 5.1-5 .N, the output (N + l) of the AND 4 logic element. (N + 1) is connected to the K-inputs of the flip-flops, the outputs of which are connected to the corresponding output buses, and the sync-inputs of the flip-flops via key to input clock pulses (TI) of the first discrete delay line 1 and the input clock schine. In addition, a second discrete delay line 7 and a switch of 8 codes are entered into the timer.

The information inputs of the switch 8 codes are connected to the input bus of interval codes, the control inputs to the third group of outputs of the storage device 2, and the outputs to the information inputs of the second discrete delay line 7. The input of the clock pulses of the second discrete delay line 7 is connected to the input bus of the clock pulses, the start input is connected to the output of the first discrete delay line 1, the initial setup input is connected to the output of the logic element OR 6, and the output is connected to the second inputs from the first to the Nth and (L4-3) -th logical elements AND 4.1-4.N and 4. (LY4-3).

The discrete second delay line 7 may consist, for example, of shift register 7.1 7.1 and multiplexer 7.2. The input of the sequential reception of register information 7.1 and the first information input of multiplexer 7.2 are connected to the input of the start pulse of the second discrete delay line 7. The remaining information inputs of the multiplexer 7.2 are connected to the corresponding outputs of the register 7.1.

In the initial state, clock pulses arrive at the clock register 7.1 shift input. At the input of the sequential reception of information and all the outputs of register 7.1, the signal corresponds to a logical “O. The control inputs of multiplexer 7.2 receive a code that provides connection to the output of the second discrete delay line 7 of one of its information inputs. The delay of the output pulse is greater, the higher the bit of the register 7.1, connected to the output of the second discrete delay line 7.

The duty cycle of the second discrete delay line 7 begins when a start pulse is received at the input of the sequential reception of register 7.1 information. A clock pulse writes a logical 1 in the first register bit 7.1. Logic 1 is shifted to higher bits of the register 7.1 by clock pulses until a pulse appears at the output of discrete delay line 7, which then goes through the external circuits to the R input of register 7.1 and zeroes it. Zeroing occurs on the decline of the pulse at the R-input. The circuit returns to its original state.

The proposed timer works as follows.

In the initial state, the control counter 3 is in the state "O. The output signals of the memory device 2 are determined by the address code from the control counter 3 and the control input bus. The information inputs of the first discrete line 1 delay from the output of the storage device 2 receives the delay code. The control inputs of the switch 8 codes from the output of the storage device 2 receive control signals that connect the interval code code to the information inputs of the second discrete zero delay code line 7 from the input bus of the code. At the inputs of logic elements And 4 from the storage device 2 receives a logical signal "O. At the input of the clock pulses of the device receives clock pulses.

The duty cycle begins after the arrival of a start pulse. The trigger pulse, coming from the input of the device, passes through the logic element OR 6, performs the initial installation of discrete lines 1 and 7 delays in accordance with the codes on their information inputs and increases the contents of the control counter 3 by "1.

After the initial setup, the duty cycle of the first discrete delay line 1 begins, the address code at the input of memory 2 is changed, and at the outputs of the last delay code and control signals to AND 4 and switch 8 codes are changed. The control signals provide a connection to the output of the second discrete line 7 of the delay 1 of the trigger input 5.1 through the logic element AND 4.1 of the logic element OR 6 through the logic element I4. (M + 3). In addition, the control signals from the output of the storage device 2 provide connection to the information inputs of the second discrete line 7 of the delay code of the interval equal to "O."

At the end of the operating cycle, the first discrete delay line 1 outputs a delayed pulse that passes without delay (not for one clock cycle) through multiplexer 7.2 to the output of the second discrete delay line 7. The impulse from the output of the second discrete delay line 7 is fed through the logic element AND 4.1 to the J-input of the trigger 5.1, allowing the setting to the state "1. A clock pulse arriving at the synchronization input of trigger 5.1 sets it to the state "1.

In addition, the pulse from the output of the second discrete delay line 7 through the logic element AND 4. (N + 3) and the logic element OR 6 makes the initial setting of the first discrete delay line 1 in accordance with the code on its information inputs and increases the contents of the control counter 3 to "one.

After the initial setup, a new cycle of operation of the first discrete delay line 1 begins, the address code at the input of memory 2 is changed, and the delay code and control signals to the AND gates and switch 8 codes are changed at its outputs. The control signals provide a connection to the output of the first discrete delay line 1 for the K inputs of the triggers, and for the output of the second discrete line 7 the delays of the 1st input of the trigger 5.2 and the logic element OR 6, as well as the code of the interval to the information inputs of the second discrete delay line 7.

At the end of the operating cycle of the first discrete line 1, the delay of the pulse with its

the output starts the second discrete delay line 7 and enters through the logic element AND 4. (N + 1) to the K-inputs of the triggers, allowing them to be set to the state of “O. On the decline of the clock pulse trigger 5.1

Q is set to the state of "O, and the remaining triggers 5.2-5.N do not change their state, remain in the state of" O.

The pulse at the output of the second discrete delay line 7 appears with a delay relative to the trigger pulse.

5 at the entrance of this line. The delay depends on the code on the information inputs of the second discrete delay line 7 (Fig. 2, the delay value is equal to one clock cycle).

The impulse from the output of the second discrete LII 7 delay enters through the logic element AND 4.2 to the 1-input of trigger 5.2, allowing the setting to the state "1. By decay of the clock pulse, trigger 5.2 is set to state "1.

5 In addition, the pulse from the output of the second. discrete delay line 7 through the logic element AND 4. (N + 3) and the logic element OR 6 performs the initial installation of the first discrete delay line 1, increases the contents of the counter 3

0 control to “1” and makes the initial setting of the second discrete delay line 7. The initial installation of the second discrete delay line 7 occurs on a pulse decay.

Thus, at output 1, it terminates 5 with the formation of a pulse in duration (a decay is formed), and at output II a pulse front is formed and the formation of a pulse duration begins. The interval between the drop of the pulse at the output I and the front of the pulse at the output II is equal to the number of delay ticks generated by the second discrete delay line 7 (in Fig. 2, one tick). The minimum number of delay ticks can be zero. Maximum number of cycles

g should overlap the recovery time of the timer (Fig. 2, te).

After the initial installation, a new duty cycle of the first discrete delay line 1 begins. In accordance with the code of the control 3, the control outputs 2 of the memory device 2 are set to control signals that block the logic elements 4.1-4.N, 4. (N + 3), unlock the logic elements AND 4. (Nf- -f-1) , 4. (N + 2) and connect to the information inputs of the second discrete line

5 7 delay code interval, equal to "O. As a result, a pulse from the output of the first discrete delay line 1 ensures the initial setting of the counter 3

control and, having passed through the discrete delay line 7, provides the initial setting to " Triggers 5. " The device returns to its original state.

A new working cycle starts at the moment when a trigger pulse is received at the input of a logical element OR 6.

The size of the time intervals and the order of the output pulses of the programmable multichannel timer in a new cycle depends on the signals that are set on the input control bus and the input bus of the interval codes,.

Claims (1)

Invention Formula A programmable multichannel timer containing the first discrete delay line, (NfS) AND gates, a memory device, a control counter. M triggers, an OR logic element, the first input of which is connected to the input trigger bus, the second input to the output (N- | -.3) -ro of the logical element And, and the output to the input of the initial installation of the first discrete delay line and the counting input of the control counter, the installation input to the initial state of which is connected to the output of the (N + 2) -ro logical element And, and counter outputs and connected to the first group of address inputs of the memory devices, the second group of address inputs of which the input is connected to the control bus, the first group of outputs is connected to infor0 the first discrete delay line has the main inputs, and the second group of outputs is connected to the first inputs of the AND gates, the second inputs (N + l) -ro and (N + 2) -ro of the AND gates, are connected to the output of the first discrete delay line, the outputs of the logic elements And connected to the corresponding 1-inputs of triggers, the output of the (N + l) -ro logic element I is connected to the K-inputs of the triggers, the outputs of which are connected to the corresponding output buses, and the synchronization inputs of the trigger are connected to the input of the clock pulses of the first discrete delay line and an input bus clock pulses, characterized in that, in order to increase the accuracy of forming small time intervals between output pulses by reducing the recovery time, a second discrete delay line and a switch are introduced into it, 0 information inputs of which are connected to the input slider of interval codes, control inputs are connected to the third group of memory outputs, and switch code outputs are connected to the information inputs of the second discrete delay line, the clock input of which is connected to the clock input strip, the start input is connected to the output of the first discrete delay line, the setup input Q is connected to the output of the logical element OR, and the output is connected to the second inputs from the first to the N- and (M + 3) -th logical elements I.