SU1751797A1 - Data receiving device - Google Patents

Abstract

The invention relates to mechanical engineering and can be used to receive information represented by a serial binary code, in particular in systems for collecting and processing information. The purpose of the invention is to increase the reliability of the device. The device contains a shift register, a pulse counter, an RS flip-flop, element I. A device for receiving information ensures reliable reception of information with a small duration of information signals without additional requirements for the speed of elements and with minimal hardware costs 2 or less

Description

The invention relates to telemechanics and can be used to receive information represented by a serial binary code.

A device for receiving a serial code is known, comprising a shift register, an information input, a zero setting input and a clock input.

A prerequisite for the reliable recording of information in the shift register is the presence in the first bit of the received code sequence of a unit (marker). When this restriction is removed, the reception of information becomes unreliable.

The closest in technical essence to the present invention is a device that receives information in the form of a serial binary code. The device contains a shift register, the information input of which receives the code parcels from the output of the unit selector.

The synchronization input of the shift register is connected to the output of the element I, the inputs of which in turn are connected to the bit outputs of the pulse counter so that the signals at the output of the element AND appear at the times corresponding to the middle part of the information pulse Number of bits of the pulse counter (t ) is chosen large enough to increase the reliability of writing the code signals to the shift register.

The duration of the code parcels is equal to the time interval allocated for the transmission of one bit of the code sequence.

In practice, there are cases when the unit premise of a code sequence is represented by short pulses, the duration of which is comparable to the period of the clock pulses, and the period of the code signals is several periods of clock pulses.

Reception of such signals in a known device becomes unreliable due to a mismatch of signals at the synchronization input of the shift register with information signals.

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The purpose of the invention is to increase reliably receiving information for any duration of a single packet of a serial binary code.

The goal is achieved by the fact that in a device containing a shift register, a pulse counter, an AND element, an RS flip-flop, an S-trigger trigger are connected to the setup input of the initial state of the pulse counter and an information input of the device, the R-trigger input is connected to the element output And, the inputs of which are connected to the corresponding bit outputs of the pulse counter. The output of the RS flip-flop is connected to the information input of the shift register, the synchronization input, the shift register is connected to the last bit output of the pulse counter.

The difference between the proposed device and the known one is that the information input of the shift register is connected to the output of the RS flip-flop, whose S input is connected to the information input of the device and is also connected to the installation input of the initial state of the pulse counter, the last bit output output of which is connected to the input synchronization of the shift register, the corresponding bit output outputs of pulse counters are connected to the inputs of the element I, the output of which is connected to the R input of the RS flip-flop.

FIG. 1 shows a block diagram of the device; in fig. 2 - timing diagrams for the operation of the device.

The device contains a pulse counter 1, a shift register 1, an RS flip-flop 3 and an element 4. The device information input 5 is connected to the input 6 of the initial state setting of the counter 1 and the S input of the trigger 3. pulses, the output of the last digit of counter 1 is connected to the synchronization input of register 2. The information input of the latter is connected to the output of the RS flip-flop, the R input of which is connected to the output of the AND 4 element, whose inputs are connected to the corresponding discharge outputs of the counter 1, the outputs of register 2 ow you a device outputs,

The device works as follows.

The information input 5 of the device receives the signals of the code sequence. Code sendings that make up a code combination and can take values of 0 or 1, follow with a period Tc. At the same time, they can coincide in time or with the first half-period of signals

clock frequency (Fig. 2a, b), or with the second half-period (Fig. 2a, g).

Single parcels are set to the initial state, for example, zero,

pulse counter 1 (Fig. 2c, d, h, i) and state 1 - RS flip-flop 3 (Fig. 2e, l).

The clock frequency signals following the period Tm are fed to the counting input 7 of the counter 1 pulses. The counting factor

counter 1 is equal to the ratio of the values of pe-. Periods of repetition of the Tc code sendings and clock pulses Tt.t.

X Tc / Tm, where N is an integer. For the diagrams in FIG. 2

N 4.

The repetition period of the counter signals at the last bit output of the counter is equal to the repetition period of the code parcels.

The pulses generated by the output of the AND 4 element (Fig. 2e, k) return the trigger 3 to the zero state, preparing it to receive the next sending of the code sequence.

Due to the simultaneous installation of the signals of the unit code sendings of the counter 1 to the initial state and the trigger 3 to the state 1, the signals at the output of the last digit of the counter, their leading edges

(Fig. 2d, i), arriving at the synchronization input of the register 2, always coincide in time with the signals arriving at the information input of the shift register 2 from the output of the trigger 3 (Fig. 2e, l), which ensures reliable recording of information in the register 2.

Thus, the proposed device for receiving information through the introduction of links between elements

Claims (1)

device provides higher reliability of receiving information. An apparatus for receiving information, comprising a pulse counter, a counting input which is the clock input of the device, the bit, except the last one, the outputs of the counter are connected to the corresponding inputs of the element I, the RS flip-flop and the shift register, the outputs of which are the outputs device, characterized in that, in order to increase the reliability of the device, the S input of the trigger is combined with the input of the initial installation of the pulse counter and is the information input of the device, the R input connected to the output of the element I, and the output to the information input of the shift register, the synchronizing input of which is connected to the last bit output of the pulse counter. iT 1