SU1727118A1 - Device for information input - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter into the processing means of processing data of multi-channel information accumulated during complex experiments. The aim of the invention is to expand the functionality of the device by providing cyclical output of relevant data. The device contains a block of drivers 1, a single vibrator 2, the first element NO 3, the first element AND 4, the first 5 and second 6 switches, a decoder 7, a channel counter 8, a second element AND 9. an information selection block 10, a control block 11, a trigger 12, the third element AND 13, the memory block 14, the OR element 15, the second 16 and the third 17 NOT elements, the comparison circuit 18, the address register 19, the address counter. 2 Il.

Description

w

&

The device relates to automation and computer technology and can be used to enter into the processor means of processing data of multi-channel information accumulated during complex experiments.

The aim of the invention is to expand the functionality of the device by providing cyclical output of relevant data.

FIG. 1 shows a block diagram of the device; in fig. 2 shows a temporary diagram of his work.

The device contains a block of drivers 1, a single vibrator 2, a first element H E 3, a first element AND 4, a first 5 and a second 6 switches, a decoder 7, a channel counter 8, a second element I 9, an information selection block 10, a control block 11, a trigger 12 , the third element And 13, the memory block 14, the element OR 15, the second element is NOT 16,

the third element is NOT 17, the comparison circuit 18, the address register 19 and the address counter 20.

The device works as follows

The information inputs of the device receive multi-channel information, presented in the format of a personnel structure. The frame information structure is a sequence of parallel Binary codes arriving on separate input channels. Each is binary and the code corresponds to a specific input channel, which is synchronized by the TC synchronization signal. The frame synchronization signal of the CS synchronizes the sequence of binary codes and their TC signals in accordance with the number of channels. The CS is fed to the input of the device simultaneously with the first signal of the vehicle, i.e. to the channel in which the information of the first measuring signal is located. .

P CE VI

00

With the arrival of the CS signal, the channel counter 8 is set to zero, and the first delayed single-selector 2 with the TC signal is set to one, and before the next CS signal arrives, the counter 8 counts the TC signals, and the decoder 7 produces single and decimal states of the counter 8, from which the switch Ea 5 and b selects any of the channel numbers, for example, the 1st channel of the 64-channel information frame. In this case, through the 1st channel, information, which characterizes an external impact, whose responses for a time (see Fig. 2) are present at the inputs of all other primary transducers in real experiments and tests, enters the device. The time (t2-ti) during which an impact takes place is accompanied by a ready signal from the TOT input of the device. From the output of the first element H E C, the GOT signal allows the sync signal of the selected 1st channel to pass through the second element 9 (VD No. 4) to the control input of the information selection circuit 10, the information inputs of which are at this time signals from i-ro channel. Data from the 1st channel is accessed via the circuit 10. On the additional outputs of the device and on the information inputs of the memory block 14 (East No. 6, 7). The recording enable input of the memory 14 when a signal is available from the control unit 11 receives a recording enable signal, and the clock input of the memory unit receives a signal from the i-ro channel (E 12) at which time information from the i-ro channel is recorded in memory block 14. Permission for receipt of a clock signal to the memory block input is generated by trigger 12 (V, Mg 10) and AND 13 element. For this, control unit 11 is on the leading edge of the GOT signal ( time ti), a signal is generated (H. No. 8), which sets the trigger 12 into one state, which is maintained until completion of the TOT signal when the block 11 is generated on the falling edge signal of the signal (E №9), sets the trigger 12 into the zero state.

Thus, in time (ta-ti), all 1st channel codes received at the input will be entered through block 10 into memory block 14, and will also be located at the additional output of the device. At the same time (ta-ti), all signals of the 1st channel TC will be counted by the address counter 20, which is set to the initial state by the signal produced by the control unit 11 at the beginning of the TOT signal (input

in block 20 through the elements OR 15, c. D. number 13). At time t2, when the lifetime of the GOT signal ends, trigger 12 prohibits the arrival of clock signals at

the memory block 14, and the signal from the control unit 11 (ID number 9) information from the address counter 20 is entered into the address register 1.9, and the address counter 20 is reset to the next counting of the i-ro channel signals (Part No. 14). In the next cycle of counting the signals of the TS of the 1st. the channel by block 20, the signals of the 1st channel TC will no longer arrive at the clock input of the memory block 14, since the trigger 12 will find 5 seconds in the zero state (the GOT signal has ended). The output states of the counter of address 20 are sent to the address inputs of memory 14, according to which, if there is a GOT signal (write permission on the control input of block 14) to the memory block. codes were entered from the i-ro channel, and in the absence of the GOT signal (read permission at the control input of block 14} from the memory block in accordance with the addresses from block 20

5, the information is fed to the additional output of the device, i.e. the additional output of the device is continuously received code from the i-ro channel in accordance with the time cycle (). End of output queue0. of the i-ro data channel from memory block 14 ends when the contents of block 20 in the address register 19 entered at the end of the GOT signal are compared with the current value at the output of block 20, which

5 is carried out by the comparison element 18, at the output of which, at the time of the comparison, a signal is generated (H. Ns 16,17), which sets the address counter to the initial, initial state each time. So be it

0 occurs until the next TOT signal arrives at the device input.

Formula of the invention — An information input device containing a block of drivers; information outputs of which are information outputs of the device, one-shot, OR element, first, second and third elements AND, first and second

0 switches, a decoder and a channel counter, the outputs of which are connected to the inputs of the decoder, the outputs of which are connected respectively to the inputs of the first and second switches, the outputs of which are connected respectively to the first and second inputs of the first element AND, which is , in order to expand the functionality of the device by providing cyclical output of relevant data, the device is inserted

the first, second and third elements of NOT, information selection block, control block, trigger, comparison circuit, address register and address counter, the device’s information inputs connected to inputs of the information selector block and driver unit, whose frame synchronization input is connected to frame input synchronization of the device and the reset input of the channel counter, the clock input of which is connected to the resolution input of the driver unit and the output of the one-shot, the input of which is the clock synchronization input of the device, the input the device readiness signal is connected to the input of the control unit and the input of the first element NOT, the output of which is connected to the first input of the second element AND, the second input of which is connected to the outputs of the first element AND, the second input of the third element AND and the counting input of the address counter, and the output connected to The input input of the information selection unit, the outputs of which are additional information outputs of the device and connected to the information inputs and outputs of the block, memory whose address inputs are connected to the first group oh comparison circuit inputs, counter outputs

address and inputs: the address register whose outputs are connected to the second group of inputs of the comparison circuit, the output of which is connected to the input of the third element NOT, the device of which is connected to the third input

an OR element whose output is connected to the reset input of the address counter, and the first input is connected to the reset input of the trigger, the second input of the control unit, the clock input of the address register and the second input

an NOT element whose output is connected to the enable input of the address register, the reset input of which is connected to the first output of the control unit, the second input of the OR element, and the trigger setup input,

the output of which is connected to the first input of the third element I, the output of which is connected to the clock input of the memory unit, the recording resolution input of which is connected to the third output of the control unit.

Claims (1)

Claim· A device for inputting information, comprising a block of formers whose information outputs are information outputs of the device, a single vibrator, an OR element, first, second and third AND elements, first and second switches, a decoder and a channel counter, the outputs of which are connected to the inputs of the decoder, the outputs of which are connected respectively the inputs of the first and second switches, the outputs of which are connected respectively to the first and second inputs of the first element And, resulting in that, in order to expand the functional due to the cyclic output of the corresponding data, the first, second and third elements NOT, an information selection unit, a control unit, a trigger, a comparison circuit, an address register and an address counter are introduced into the device, and the information inputs of the device are connected to the inputs of the information selection unit and a shaper unit, the frame synchronization input of which is connected to the frame synchronization input of the device and the channel counter reset input, whose clock input is connected to the resolution input of the ph controllers and the output of a one-shot, the input of which is the input of the clock synchronization of the device, the input of the device ready signal is connected to the input of the control unit and the input of the first element NOT, the output of which is connected to the first input of the second element And, the second input of which is connected to the outputs of the first element And, the second input the third element And and the counting input of the address counter, and the output is connected to the control input of the information selection unit, the outputs of which are additional information outputs of the device and the connection are connected with information inputs and outputs of a block, memory, the address inputs of which are connected to the first group of inputs of the comparison circuit, the outputs of the address counter and the inputs of the address register, the outputs of which are connected to the second group of inputs of the comparison circuit, the output of which is connected to the input of the third element NOT, the output of which is connected to the third input of the OR element, the output of which is connected to the reset input of the address counter, and the first input is connected to the reset reset input, the second input of the control unit, the clock input of the address register and the input of volts of the second element NOT, the output of which is connected to the enable input of the address register, the reset input of which is connected to the first output of the control unit, the second input of the OR element, and the trigger input, the output of which is connected to the first input of the third AND element, the output of which is connected to the clock input of the block a memory whose recording permission input is connected to the 7th output of the control unit. FIG. 2