SU1645956A1 - Logic units checking and fault diagnosing device - Google Patents

Abstract

The invention relates to computing and can be used to monitor the health and troubleshoot logic blocks. The purpose of the invention is to increase the reliability of the control. The invention permits the search and detection of faults in logic blocks as well as in control circuits by using an additional shadow reversing shift register. The device contains the first and second demultiplexers, the first multiplexer, the synchronization unit, m logic blocks, a comparison unit, a mode setting unit, m shift registers, a second multiplexer, and a buffer register. 13 il. at

Description

The invention relates to computing and can be used in systems for monitoring the performance and troubleshooting of logic blocks.

The purpose of the invention is to increase the reliability of the control.

Fig. I shows a block diagram of the device; figure 2 - diagram of the logic unit; Fig. 3 diagram of the switch block; figure 4 - diagram of the synchronization unit; in fig. 5 is a comparison block diagram; Fig. 6 is a timing chart of the arrival of clock signals; 7-10 - timing charts of the device; Fig.41-13 - examples of loading information in the registers.

The device contains the first 1 and second 2 demultiplexers, the first

multiplexer 3, synchronization unit 4, m logical blocks 5, comparison unit 6, mode setting unit 7, shift registers 8 m, second multiplexer 9, buffer register 10, fault indication output 11 and device clock input 12, outputs 13-17 and input 18 synchronization unit 4, inputs 19-23 and outputs 24-26 of the buffer register 10, inputs 27 and 28 and output

29 first multiplexer 3, inputs

30 and 31 and the output 32 of the second multiplexer 9, the inputs 33-37 and the outputs 40 of the register 8 the input-output 41, the inputs 42-44 and the output 45 of the logic unit

.

5, inputs 46 and 47 and outputs 48 of the first demultiplexer 1, inputs 49 and 50 and outputs 51 of the second demultiplexer 2, inputs 52-56 and output 57 of the comparison unit 6, outputs 58-61 of the mode setting unit 7.

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Logic block 5i (iel, m) contains multiplexers 62 and 63, block 64 of memory elements, input 65 of the state record, control input 66 and input 67 and 68 of the multiplexer data - 63, input 69 of the state record, data inputs 70, information input 71 of block 64, inputs 72-74 of multiplexer 62, output 75 of blocks 5.v

Yelok 7 task mode is made on, 79 keys; (j-1,1), .n), 8C, 82K (, r), 83-86 and has exit 87-97.

Sync block 4 contains

triggers 98-103, elements OR 104-106, elements AND 107-124, - counters 125-127, circuits 128-129 Comparison, elements NOT 130-132, encoders 133-134, generator 135 clock pulses with outputs 136 and 137, the decoder 138 with the outputs 139-144, the register 145 number of shifts, the outputs 146-150 and the inputs 151-158 block,

Comparison unit 6 consists of a multiplexer 159, elements OR 160 and 161, elements NOT 162 and 163, comparison circuit 164, element AND 165 and has an error signal output 166 / inputs 167 of standard signals, inputs 168-170 of mode signals, input 171 the enable signal of unit 6, the input 172 of the signal Reset and the output 173 of the signal the end of the device.

Demultiplexer 1 is intended

for transmitting a control signal from output 15 of block 4 to input 42; selected block 5 (synchronization of recording of test sets to logic block 5;). A demultiplexer I controls the signal to input 47 from output 61 of block 7.

The demultiplexer 2 is used to transmit a control signal from the output 14 of block 4 to the input.37; the selected register 8, (synchronization of the recording of information in the register 8;) and is controlled by the signal received at the input 50 from the output 16 of the block 7.

The multiplexer 3 is used to transmit signals from the outputs 40j of the registers 8 to the input 23 of register 10. The multiplexer 3 controls the signal to the input 27 from the output 61 of block 7.

Block 7 is designed to set the modes of operation, initial states and start the device.

The multiplexer 9 serves to transmit signals from outputs 39 of register 8 to input 19 of register 10 and is controlled by a signal input to input 30 from output 61 of block 7.

The shift registers and the buffer register 10 function as reverse shift registers and operate in the following modes: information shift to the right, information shift to the left, receiving information from logical blocks 5 {(for registers 8;) and from output 59 of block 7 (for buffer register 10 ). The operating mode code of registers 8 is set at output 16 of block 4, and register 10 at output {7 of block 4. Synchronization of operation of registers 8} is performed by the demultiplexer 2 on signals from output 14 of block 4 and output 61 of block 7. Synchronization of register 10 - on the signal at output 14 of block 4.

Comparison unit 6 is designed to analyze the control information received from output 26 of register 10 by comparing it with information coming from outputs 58 and 59 of unit 7. The result of the analysis is a signal of malfunction or health of information transfer circuits at device output 11.

The timing diagram of the formation of clock signals by the clock pulse generator 135 is shown in FIG.

Logic block 5 operates in two modes.

The mode that provides the basic functions of the logic blocks - the mode of operation.

At input 44j (input 74 of multiplexer 62 and input 66 of multiplexer 63), a control signal (e.g. Im) is supplied. The multiplexer 62 permits the passage of the signal through the input 72 (65) and prohibits the passage of the signal through the input 73 (42,) to the input 69 of the block 64 of memory elements. The multiplexer 63 permits the passage of information on input 67 (70) and permits the passage of diagnostic information from input 68 (43;) to information input 71 of block 64 of memory elements. At input 65, a state recording signal is supplied, for example, from the output of the firmware control block of the device under test. Informational interaction of logical blocks

5f is carried out on the inputs-outputs 41. (inputs 70; and outputs 75j).

The mode that provides diagnostics and troubleshooting in logical blocks - Diagnostics mode

A control signal (for example, O) is supplied to input 44 (input 74 of multiplexer 62 and input 66 of multiplexer 63). The multiplexer 62 blocks the passage of the signal through the input 72 (651) and allows the passage of the signal through the input 73 (42j) to the input 69 of the block 64 of memory elements. The multiplexer 63 prohibits the passage of information from the input 67 (70j) and allows the passage of diagnostic information from the input 68 (43) to the information input 71 of the block 64 of memory elements. It is forbidden to perform basic functions by a logical unit. At entrance 42 | a state recording signal is given

The synchronization unit 4 is designed to form complexes of control signals that organize the operation of the device in various predetermined modes.

Preliminarily, on keys 82 to, the code of the number of the served logical block 5 is dialed;, on keys 8C and 80 - the test and reference information.

One of the keys 85, 86, 76 and 77 is set to state 1, set to 1 one of the flip-flops 98 101 on the arrival of the clock signal C1 from the output 136 of the generator 135. The signal from the output of the flip-flops 98-101 passes through the OR 104 element.

With the arrival of the signal, the key 83 sets the trigger 103 to state I. It enables the counter 125 (clock signals C2), the signals from the output of which are fed to the input of the decoder 138. At the outputs 139-144 of the decoder 138, signals are generated that write to the register 10 (output signal 139, exit code 17, I in FIG. 7-10), transferring information from register 10 to register 8 in the forward direction (output signal 140, codes at outputs 16, 17, II in FIG. 7-10), write to logic block 5- (signal at output 141, pulse at output 15; III on 1FIG.7-10), write to register 8- (signal l at the outlet 142, the code output 16, IV 7-10), the information transfer from register to register 8f 10 in the opposite

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Nominal direction (signal at output 143, codes at outputs 16, 17; V in Figures 7-10), termination of operation and fault detection (signal at output 144 (142), VI, Fig.7-10).

the generation of codes controlling the operation modes of registers 81 and 10 1 (outputs 16 and 17) is performed under control of signals from the outputs of the trigger 98-101 of the modes, signals from the outputs 139-144 of the decoder 138, and the signal from the output of the trigger 102 of the offset correction.

The recording signal in block 5- (output 15) is generated in the mode of recording test sets in logic block 5.1 in the third cycle of operation of the decoder 138 (output 141) and is gated by the clock signal CI.

The synchronization signals of registers 10 and 8j (output 14) are removed from output 136 of generator 135. The number of 5 information shift cycles in registers 10 is determined by the contents of register 145 and counters 126 and 127, the signals from which are fed to the circuits

1 28 and I 29 comparisons and from their outputs through 0 elements AND 113 and 112 to control element AND 107. When signal 1 is present at output 140 (143), at the output of element OR 105, a signal is generated that prohibits the passage of sync signals to the input of counter 125 to those until the contents of counter 126 (127) compare with the contents of the register 145.

The signal of the end 0 operation in one of the modes (output 13 (147)) is generated under control of the signals from the outputs of the decoder 138 and the triggers 98-101 upon completion of the operation in each of the modes. The signal from the output 5 of the element OR 106 is inverted on the inverter 132 and prohibits the passage of the clock signals C2 to the input of the counter 125.

Information is transferred from buffer 0 register 10 to registers 8- from outputs 24 and 25 directly to inputs 34 and 36, and receiving information from buffer register 10 from registers 8 to inputs 19 and 23 5 from outputs 40 {and 39 {via multiplexers 3 and 9 respectively.

The device is designed to ensure the operability of logical blocks 5 / by entering

five

test sets using buffer register 10 and registers 8} to selectable logic block 5}, read information from logical blocks 5, and compare the read information with the reference; testing the operability of information transmission circuits in logical blocks 5 (registers 10 and 8, |); fault detection in the process of transferring information to logical blocks 5; (in registers 8;).

The device operates in the following modes.

1 Putting test cases into logical blocks 5.J

This mode ensures the initialization of the memory elements of the logical block 5y. The timing diagram of the device in this mode is presented in Fig.8. The operation of the device in this mode begins with the installation of the trigger 102 in state 1 by key 84 (previously, the trigger 98 is set to state 1 by a signal from key 85, key i 82 is assigned number i of the selected logical block 5j, on keys 81.- test information, and on keys 79. - number of shifts At output 14, a signal is written to record information in the buffer register 10, while simultaneously generating a code at output 17 of block 4 (input 21 of register 10), allowing writing to buffer register 10. Then, at inputs 16 and 17 of block 4 shift codes are given information left (or right) in register 8 | and shift information to the right (or left) in buffer register 10 (Fig. 1). By the synchronization signals received at input 22 of buffer register 10 and input 37; shift register 8j from the output 14 of block 4, moving

information from buffer register 10 to register 8 {Thereafter, the input 42 of logical block 5J is given a signal from output 15 of block 4, which is used to record information in logical block 5.

2. Reading control information from block 5; and check block 5 ,. This mode provides for obtaining information on the state of control points of the logical block 5j and comparing this information with the reference one. The timing diagram of the device in this mode is presented in Fig.8.

The operation of the device in this mode begins with the installation of the trigger 102 in state 1 by key 84 (previously, trigger 99 is set to state 1 by a signal from key 86, and key 82K dials i of the selected logical block 5, on keys 80.J. , and 79 keys on the number of shifts). Output 14 generates a write signal to register 8 while simultaneously generating a code at output 16 of block 4 (input 35 / register 8 |), which allows writing to register 8j. At the inputs 16 and 17 of the device, codes are provided that allow information to be shifted to the left (or right) in per h 8; and shifting the information to the right (or left) in the buffer register 10. According to the synchronization signals received at the input 22 of the buffer register 10 and the input 37, j of the register 8j from the output 14 of block 4, the information from the register 8 is transferred to the buffer register 10. Thereafter the obtained information is removed from the output 26 of the register 10 and is used to analyze the performance of the logic block 5.1, by comparison with the standard.

The information from the output 26 of the register 10 is fed to the first input of the comparison circuit 164 (to the input 55 of block 6), to the second input of which the information of the reference passes through the multiplexer 159 (with the signal 1 to the control input coming from the output of the trigger 99). If the input data are equal (which signals the correct operation of block 5), the output signal O is generated at the output of the comparison circuit 164, otherwise signal 1 (which signals malfunctioning of block 5). From the output of circuit 164, the error signal passes through AND 165 to output 166. The error signal at output 166 of block 6 can occur only in the Control mode and in the absence of the Reset signal.

3. Monitoring the performance of registers 8 and the buffer register 10.

The timing diagram of the operation of the device in this mode is presented in Fig.9.

On keys 81. a test case is dialed (for example, a code consisting of one 1 (O) symbols or a chess code). The operation of the device in this mode begins with the installation

trigger 102 to state 1 with key 84 (pre-trigger 100 is set to state 1 by signal from key 76, key i 82 of the selected shift register 8 is dialed;, and keys 79j - the number of shifts). The output 14 generates a write signal to the buffer register 10, while simultaneously forming the code at the output 17 of block 4 (input 21 of register 10). Allowing writing to the buffer meter 10. Then, the outputs 16 and 17 of block 4 are fed codes permitting information shift to the left (or right) in register 8 and information shift to the right (or left) in buffer register 10. According to the synchronization signals received at input 22 of buffer register 10 and input 37 j of shift register 8, output 14 of block 4 , information is transferred from buffer register 10 to register 8j and further to buffer register 10. After that, the information obtained is removed from output 26 of register 10 and is used in block 6 to analyze the performance of register 8 and buffer register 10.

The information from the output 26 of the register 10 is fed to the first input of the comparison circuit 164 (to the input 55 of block 6), to the second input of which the information of the test set passes through the multiplexer 159 (with the signal O at the control input coming from the output of the trigger 99). If the input data is equal (which indicates that the register 8j and register 10 are working properly), a signal O is generated at the output of the comparison circuit, otherwise a signal 1 (which signals the malfunctioning of registers 8; and 10). From the output of the circuit 164, the error signal passes through the element AND 165 to the output 166. The error signal at the output 166 of block 6 can appear only in the Control mode and in the absence of the Reset signal,

4. Troubleshooting in register 8 ;.

The timing diagram of the operation of the device in this mode is presented in Fig.9.

The operation of the device in this mode begins with setting the trigger 102 to the state 1 by key 84 (previously, the trigger 101 is set to state 1 by the signal from the key

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77, and on keys 82k, the number i of the selectable shift register 8 is dialed, on the keys 81 j test information, and on the keys 79. the number of shifts). The output 14 generates a write signal to the buffer register 10 while simultaneously forming the code at the output 17 of block 4 (input 21 re .Q of the horn 10), which allows writing to the buffer register 10. The outputs 16 and 17 of block 4 are given codes allowing the information to shift to the left (or right) in register 8 and information shift

jc to the right (or left) in the buffer register 10 (figure 1). According to the synchronization signals received at the input 22 of the buffer register 10 and input 37; shift register 8j from the output of block 14

20 4, information from the buffer register 10 is moved in the direction of register 8 for the required number of bits. Then, at the outputs 16 and 17 of the device, codes are sent

25 shifting information in the opposite direction - to the right (or to the left) in register 8, and to the left (or to the right) in the buffer register 10. By the synchronization signals arriving at the inputs

30 22 and 37; from output 14 of block 4, information is transferred from register 8, in the direction of the buffer register 10 to the same number of bits. After that, the resulting in-

The formation is removed from the output 26 of register 10 and is used in block 6 of the comparison to analyze the malfunction. In this case, the fault of register 8 of type open or short to ground is

4Q lx according to the available information (test set; information read from register 10; number of shift cycles) is localized with an accuracy of one bit (provided that the right job is 45 register 10).

Shift register fault localization 8 | can be seen on the example of a fault type of short circuit to the ground S-ro bit.

JQ This fault is localized.

on a test set consisting of symbols 1 (FIG. 11). The test set through the buffer register 10 is transferred to the register 8 "(for example, when

shifting it to the left) by one bit. Then reading the information of register 8; the shift to the buffer register 10 is performed in the opposite direction. In block 6, the test suite compares

с с с ё information. The malfunction signal is not generated (not good condition in the S-M bit).

Work in this mode repeats with a few more times. The amount of shift. This information is increased by one each time. After the information is transferred to register 8 {from register 10 (with the number of shifts equal to S), the value of bits of register 8 is shown in Fig. 12. After reading the information from register 8 into register 10, the value of the bits of register 10 is shown in FIG. In block 6, the test suite is compared with the information received. Since the test set v the received information does not match, a malfunction signal is generated, indicating a malfunction of the 1st bit of register 8; .

With a more complex implementation of block 6 comparison, it is also possible to detect faults in register 10.

Claims (1)

Invention Formula A device for monitoring and diagnosing malfunctions of logic blocks containing the first and second demultiplexers, the first multiplexer, the synchronization unit, the mode setting unit and the comparison unit, the output of which is the device indication output, and the first and second information inputs of the comparison unit are connected respectively to the first and second outputs of the mode setting block, the third and fourth outputs of which are connected respectively to the trigger input of the synchronization block and the control inputs of the first and second demultipl the first and third outputs of the synchronization unit are connected to the first synchronous input of the comparison unit and the information inputs of the first and second demultiplexers, respectively; the information outputs of the first demultiplexer are the device outputs for connecting to the inputs of the same-name control Q 0 five thirty 35 40 45 50 logical blocks, and the second synchronized input of the comparison unit is connected to the synchronous input of the device and is a synchronized input of the controlled logical blocks, characterized in that, in order to increase the reliability of the control, it contains m shift registers according to the number of checked logical blocks, the buffer register and the second multiplexer whose control input is connected to the fourth output of the mode setting block, the output of the second multiplexer is connected to the first information input of the buffer register, the information inputs of the second the multiplexer is connected to the first information outputs of the same shift registers, the first information inputs of which are connected to the first information output of the buffer register, the second information inputs of the shift registers are connected to the second information output of the buffer register, the second information outputs of the shift registers are connected to the same information inputs of the first multiplexer, the output of which connected to the second information input of the buffer register, information outputs of the second demultiplex the plexer is connected to the synchronous inputs of the same shift registers, the third information inputs and outputs of the shift registers are respectively the inputs and outputs of the device for connection to the information outputs and inputs of the same controlled logic blocks, the synchronous input of the buffer register is connected to the third output of the synchronization unit, the second output of the mode setting unit is connected to the input of the initial setup of the buffer register, the fourth and fifth outputs of the synchronization unit are connected respectively to the inputs of the register offset and a buffer register mode input, the third information output of which is connected to the third information input of the comparison block 3 I  3 S3 §five I Na § t: & & 01 VO (T J & J Na $ R .0 Fig.Z 61 oh a iTl t vO No Yag f five) / Output W generator / 35 city Exit Y37 Gengrapyuro # 5 n n n Phage. five I / y AT -t t JUUUUL JUUUULJ1 r / W wf l / / miiijoc: P / 7 # -t t / W wf l P FIG. 7 s. Phage. AT I V I. S sent by sbigig 8 register 10 when loading registers FIG. eleven Ш1 And and one n-f S-1 s sdde direction in register 8 when booting Phage. 12 01s-f $ 1 -1 - sdbiga in the register with read register 8 FIG. 13 MiJ nf f