SU1689994A2 - Apparatus for testing operative memory unuits - Google Patents

Abstract

The invention relates to static-type storage devices, specifically to the control of storage devices for their correct operation and can be used in the development, debugging and diagnostics of operational memory failures. The purpose of the invention is to expand the field of application of the device due to the possibility of controlling memory blocks with a trunk parallel interface. The device contains a generator, control signal formers, a hell counter; rez, address setting block, switches, display blocks, reset blocks, cycle counter, synchronization address selection block, address and cycle comparison block, block The invention relates to static-type storage devices, specifically to controlling storage devices for correct operation, can be used when developing, debugging and diagnosing malfunctions of random access memory devices and is an improvement of the invention auth.st. No. 1265859. formation of the operation flag, mode control units, mode indicator drivers, initial code setting unit, data inversion units, data inversion characteristic driver, data comparison unit, interrogation signal generator, start unit, transceiver unit, transmitter unit, error fixing unit, an error switching unit, a D-flip-flop, pulse distributors, a third switch control unit, an inversion control unit, a transceiver control unit. Introduced features - transceiver unit, third and fourth data inversion unit, transmitter unit, error fixing unit, error deactivating unit, D-flip-flop, pulse distributors, third switch control unit, third switch, fifth display unit, second error reset unit, second and the third mode control unit, the second, third and fourth control signal drivers, the inversion control unit, the second, third and fourth mode signature drivers, and the transceiver control unit provide m can check storage units with a standard interface DIF without involving deficient personal computers. 20 il. The purpose of the invention is to expand the field of application of the device by enabling the control of memory blocks with a trunk parallel interface. FIG. 1 and 2 are schematic diagrams of a device for monitoring RAM blocks; in fig. 2 is a block diagram of information transceivers; in fig. 4 cl with about with Ch o y 4 GO

Description

- scheme of the third block of data inversion; in fig. 5 is a diagram of the fourth block of data inversion; FIP 6 - block diagram of information transmitters; in fig. 7 is a block diagram of the fixation of errors; in fig. 8 is a diagram of the p of the display unit; in fig. 9 is a diagram of a second error reset block; in fig. 10 is a diagram of a second mode control unit; in fig. 11 is a diagram of the first pulse distributor; in fig. 12 is a diagram of the second pulse distributor; in fig. 13 is a diagram of the third switch; in fig. 14 shows circuits of the second and third control signal drivers; in fig. 15 is a diagram of an inversion control unit; in fig. 16 is a diagram of a first mode formation unit; FIG. 17 is a diagram of a second mode formation unit; in fig. 18 is a diagram of the third characteristic condition generating unit; in fig. 19 is a diagram of a transceiver control unit; in fig. 20 is a temporary diagram of the operation of the device.

The device contains (FIG. 1, 2) clock generator 1, first driver 2 control pulses, address counter 3, address setting unit 4, first switch 5, second switch 6, second address indication unit 7, first reset unit 8, counter 9 cycles, synchronization address selection block 10, address and cycle comparison block 11, operation feature generating unit 12, mode control unit 13, mode feature generating unit 14, first starting code setting unit 15, pseudo-random code generator 16, third displaying unit 17, first block 1 8 data inversions, data inversion characteristic driver 19, second data inversion unit 20, fourth number indication unit 21, data comparing unit 22, interrogation signal generator 23, start unit 24, switching unit 25, first malfunction indication unit 26, first output 27 devices (access pulse output), the second synchronization output 28, the operation indication third output 29, the inequality signal fourth output 30 (fault symptom), the fifth group of outputs 31 of the address code, the group of information outputs 32, the first input 33 of the device (input from the inversion by addresses), the second group of inputs 34 of the device (the inputs of the read information), the communication groups (code buses 35-46, as well as individual communications 47-74.

Blocks 12-14, 19 form a local control unit with connections. FIG. 2 block 74 transceivers information, the third 76 and fourth 77 blocks of data inversion,

information transmitters block 78, error fixing block 79, error shutdown block 80, fifth indication block 81, second reset block 82, second mode control block 83, D-flip-flop 84, first pulse distributor 85, second pulse dispenser 86, control block 87 the third switch, the third switch 88, the second 89, the third 90, the fourth 91 control signal generators, the inversion control unit 92, the third mode control unit 93, the second 94, the third 95 and fourth 96 mode characteristic generation units, the receiver 97 control unit data s, the fifth block 98 forming characteristics modes.

FIG. 2 also shows the connections and inputs, the outputs of the device 99-129.

The information transceiver unit 75 (see Fig. 3) contains electronic switches, the receiving inputs of which are the group inputs 99 of the block 75, and the outputs - group outputs 102, Trunk inputs-outputs electronic

5 switches are connected to the trunk buses 100 of the transceiver unit 75. The control inputs of the electronic switches are connected to the corresponding inputs 101 and 120 of block 75. At the same time

0, input 101 provides for switching the operation mode of the electronic switches. At the potential of Log.O, electronic switches provide data reception at inputs 99 and output to trunk 100,

5 a at potential. Log.1 at input 101 receives from trunk 100 and outputs to trunk 102. At input 120, the transceiver unit is turned off, i.e. when the potential of the log. About the input 120 is resolved

0 operation of electronic switches in block 75, and at potential Log.1 at output 120, electronic switches will be in the third state (closed) and there will be a high resistance on the main outputs 100 of block 75 of the transducer 5 sensors. In the prototype, 585 AP26 microcircuits were used as electronic switches, which ensure the switching of 16-bit data information

0 The third data inversion unit 76 (FIG. 4) contains a group of EXCLUSIVE OR elements that perform the function of controlled inverters. The information inputs of the EXCLUSIVE OR elements are connected to the group of 32 odds, the other inputs of all the EXCLUSIVE OR elements are interconnected and connected to the input 103 of the data inversion unit 76. At potential Log. O at input 103, data from inputs 32 are transmitted to outputs 99 of block 76 in the forward code, and at potential Log.1 in inverse.

The fourth data inversion unit 77 (FIG. 5) contains a group of EXCLUSIVE OR elements that perform the role of controlled inverters. The information inputs of the EXCLUSIVE elements OR are connected to the group of inputs 102, the other inputs of all the elements EXCLUSIVE OR are interconnected and connected to the input 103 of the data inversion unit 77. At potential Log. O at input 103, data from inputs 102 are transmitted to outputs 34 of block 77 in the forward code, and at potential Log.1 in inverse. In the prototype of the device, blocks 76 and 77 of data inversion had 16 bits and were performed on 133LP5 microcircuits.

Information transmitters block 78 (Fig. 6) contains transmitting elements whose receiving inputs are connected to a group of inputs 31, and outputs to a group of outputs 100 of block 78. The control input of transmitting elements is connected to input 120 of transmitters block 78. At the Log.O potential at the input 120, the transmitting elements are open and provide data transfer from the inputs 31 to the outputs 100. At the potential of Log.1, the transmitting elements at the input 120 are closed and high resistance (third state) at the outputs 100 of the transmitter block 78,

In the prototype of the device in block 78 of transmitters, KR 580VA87 microcircuits were used as transmitting elements, which ensured the translation of 16-bit address information.

Block 79 (FIG. 7) contains an L-flip-flop 130, the D-input of which is connected to the input 105 of the block 79. The installation R-input of the D-flip-flop 130 is connected to the input 107 of the 79 block. block 79. The zero output of the D-flip-flop 130 is connected with the first input of the And 131 element and one of the outputs of the group 110-1 of the block 79. The second input of the And 131 element is connected to one of the outputs of the group 110-2 of the 79 and to the output of the And element -NE 132, the first and second inputs of which are associated respectively with inputs 104 and 106 of block 79. The presence of a signal The answer at input 105 is fixed in the D-flip-flop 130 with the arrival of si drove PZ / THU from input 108. Signal of no signal A response from the output of the D-flip-flop 130 is output to one of the outputs 110-1. A fault sign of the NIS ZU is fed to the input 104 and through the IS-HE element 132 under the condition of the permitting potential at the control input of the IS-HE element 132 passes to one of the outputs of the output group 110-2. Signs of

errors are combined on the element AND 131 and from its output are sent to the output 109 of the block 79. The D-flip-flop 130 in the prototype is made on the chip 133 TM2.

Block 80 off errors contains a switching element, one of the contacts of which is connected to the bus Log.1, and the other with the bus Log.O (1). The output of the switching element is the output 106 of the block 80. In the prototype device, the switching element was made on a P1TZ toggle switch.

Fifth display unit 81 (Fig. 8) contains LEDs 133, 134, the anodes of which are connected, respectively, to the inputs 110, and the cathodes are combined and connected to the voltage source + E (via resistors not shown in the diagram). In the prototype, the display unit 81 is made on LEDs ZL102.

The second error block 82 (Fig. 9) contains a switching element 135 (made in the form of a button), the middle contact of which is connected to the bus Log. O (1), and the outputs, respectively, with the installation and tangent inputs of the trigger 136, whose single output through the delay element 137 is connected to the first input of the element IS-HE 138, and the zero output to the second input of the element IS-HE 138, the output of which is connected to the output 107 of the block 82.

In the initial state, the middle contact of the switching element 135 is normally closed with its first output and normally open with the second output. In this case, the trigger 136 is set to state 1, therefore, on one of the inputs of the element IS-NE 138 there will be a single potential, and on the other - zero. Since the switching element 135 is designed as a self-returning button, after the operator presses this button, the output of the NE-NE element 138, when the button is released, will generate a negative polarity reset impulse arriving at output 107. In the prototype of the device, the switching element 135 is made on a button switch PKN2 type, trigger 136 - on a 133 TM2 chip, and 136 LN1 chips were used as a delay element 137.

The second mode control unit 83 (FIG. 10) contains switching elements 139, 140. The first and third contact of the switching element 139, the first and second contacts of the switching element 140 are connected to the bus Log.1, and the second contact of the element 139 and the third contact of the element 140 are connected bus Log. O. Moving contacts of the switching elements 139 and 140 are outputs 111, 112 of unit 83, respectively. The switching elements 139, 140 are mechanically connected and switched synchronously. In the prototype, the switching elements 139 and 140 are made on a switch of type PG2.

The first pulse dispenser 85 (FIG. 11) is provided on the delay element. The input of the delay element is the input 120 of the pulse distributor 85, and the outputs

- according to exits 114-1, 114-2, 114-3, 114-4, 114-5, 114-6, 114-7, 114-8. In the prototype of the device, a delay line of the type LZS-20-1-600 was used as a delay element (the matching elements of the input and output of the delay line are not shown in the diagram).

The second pulse distributor 86 (FIG. 12) is provided on the delay element. The input of the delay element is connected to the input 116 of the distributor 86 pulses, and the outputs

- with corresponding outputs 115-1 and 115-2. In the prototype, a delay element was made on the LMZ-0.25- 600 microline (the matching elements of the input and output delay lines are not shown in the diagram).

The third switch 88 (Fig. 13) is made on a selector-multiplexer. The first, second, third and fourth inputs of the selector-multiplexer are the corresponding inputs 114-8, 114-6, 114-7, 114-4 of the switch 88, the Fifth (inverting) and the sixth inputs of the selector-multiplexer are connected to the input 115-1 the switch 88, and the seventh and eighth inputs are connected, respectively, to the inputs 115-2 and 116 of the switch 88. The control input DC of the selector-multiplexer is connected to the input 113 of the switch 88. The first, second, third, fourth inverting outputs of the selector-multiplexer are respectively, the outputs 117, 118, 119, 105 of the switch 88. In o A sample device was used as a selector-multiplexer KP14 chip 530.

The second 89, third 90, fourth 91 drivers, control signals (Fig. 14) are made on D-flip-flops. The setup S-input of the trigger for former 89 is input 114-2. The C-flip-flop is input 118, which zeroes the R input on input 49. The D input of the trigger is connected to the Log bus .O. The trigger output is the output 121 of the driver 89.

The synchronizer trigger trigger -90 is input 119, the first R insertion input is input 117, and the second R input invoice is input 49, the D input is trigger

connected to the bus Log.1. The trigger output is the output 121 of the driver 89.

The setup S-input of the trigger of the imager 91 is input 49. Synchronized input C-input 105, an R-inlet which is turned on - input 114-1, the D-input of the trigger is connected to the Log bus, 1. The trigger output is the output 123 of the driver 91.

In the prototype of the device in the 89-91 former, triggers were used on 133 TM2 microcircuits. In order to avoid temporary overlays, the installation of flip-flops on the inputs R and S is carried out by shortened pulses. The pulse shortening circuits at the inputs of the R and S triggers in FIG. 14 not shown.

The inversion control unit 92 (Fig. 15) contains an AND element 141, an output connected to an R-S flush R-inlet inlet

142. The inverting input of element 141 is connected to input 27 of block 92, the second input is connected to the R-inlet of the counting trigger 143 and to the 112 input of the block 92. The third input of the AND 141 is connected to the setting input of the counting trigger 143 and to the input 111 of the block 92. The installation S-input of the trigger 142 is input 114-5, and the synchronous input C of the trigger 143 is input 49 of the block 92, the output of the trigger 142 is connected to exit 124 of the block 92 s

one of the inputs of the EXCLUSIVE OR 144 element, the other input of which is connected with the output of the trigger 143, and the output - with the output of 103 LOC 92. In the prototype, the devices of the trigger 142 and 143 are made on the 133 TM2 chips, and the EXCLUSIVE OR 144 is on the chip 133 LP5.

The first block 94 of the formation of the mode feature (Fig. 16) contains a digital node that implements the 2I-OR function. The first (inverting) input of the first group I is connected to the input 125 of block 94. The second input of the first group is connected to the second (inverting) input of the second group And and to the input 120 of block 94. The third (inverting) input of the second group I is connected to input 29 of block 94 In the prototype block 94 is made on the chip 133LN1; 133LR1. The third block 95 of the formation of the characteristic mode (Fig) contains the element And

145, one of the inputs of which is input 29 of block 95, the other (inverting) is input 112, and the output is connected to the inverting input of HE 146 and is output 126 of block 95. The second input of HE 146. The input element hE 146 is connected to the output 128. In the prototype, the elements AND 145 and HE 146 were executed on 133LN1, 133LPZ, 133LI microcircuits.

The third block 96 of the formation of the mode feature (Fig. 18) contains the element 2I-IL AND NOT. The inputs of element 2I-OR-NOT are the corresponding inputs 126, 121, 122, 112 of block 96, and the output is connected to output 129 of block 96. In the prototype, element 2I-OR-NO is executed on chip 133LR1.

Transceiver control unit 97 (Fig. 18) contains element 2I-OR-. One of the inputs of the first group AND element 2I-OR-NOT is connected to the first input 29 of block 97, and the other inverting - to one of the inputs of the other-group AND element 2I-OR-NOT and to the input 112 of block 97. The second input of the second group AND element 2I-OR-NOT is connected to the third input 124 of block 97, and the output is output 101.

The purpose of the individual components of the additional device is shown in FIG. 2

The information transceiver unit 75 provides the data translation when recording a group of inputs 99 into the trunk 100, which is connected to the inputs and outputs of the monitored memory unit, in the memory unit. In read mode, transceiver unit 75 passes data from trunk 100 to outputs 102 that are connected to the main part of the RAM control unit for further information analysis. The control of switching the direction of data transmission is carried out at the input 101 (D1EM). The block 75 is switched off to the third state upon receipt of Log.1 at the input 120.

The third block 76 data inversion is designed to invert the input data when writing data to the memory block when checking its performance in the Read with Modification mode.

The fourth data inversion block 77 provides the inversion of the data of the output information when reading data from the memory block while monitoring it in a mode. Reading with a modification.

Information transmitter block 78 translates address codes from address input group 31 into trunk 100. Block 78 is turned off when potential Log.1 is applied to control input 120. In this case, its outputs will be the third state, characterized by high output resistance.

Error fixing unit 79 registers signs of errors in the monitored memory block. In total, there are two signs of errors accompanying the process of information exchange between the control device and the memory unit.

Input 104 receives a symptom of malfunction (NIS ZU) from the memory block, and par 105 is a sign (OTV) of the memory block when exchanging information with the control device. The absence of an OTF feature is perceived by the error-fixing unit 79 as a failure of the memory unit. Error fixation block 79 generates error potentials at its outputs 110 and sends them to fifth

0 block 81 display.

The error shutdown unit 80 provides for the disconnection of the error sign received at the input 104 (NIS ZU error) to the error fixing unit. Sign off

5 errors are used in the error diagnostics modes of the monitored memory block. Fifth display unit 81 provides a visual indication of the occurrence of errors detected during detection.

0 no response signal (TSS) or upon receipt of an error signal (NIS ZU) from the memory block.

The error reset unit 82 generates a signal to bring the latching unit 79 to an error in its original state.

The second mode control unit 83 forms the potentials at the outputs 111,112, to control the operation of the second inverter control block 92, the third 95 and

0 of the fourth 96 characterization unit forming units and the transceiver control unit 97 when the operation mode is read Read with modification.

D-flip-flop 84 forms a pulse for the start of the first impulse distributor 85. D-flip-flop 84 is turned on so that it is self-resetting, which makes it ready for operation immediately when the supply voltage is turned on.

0 In the prototype of the device, D-flip-flop 84 is made on a 133TM2 chip.

The first 85 and second 86 pulse distributors form signals at their outputs 114 and 115 to control the operation

5 of the second 89 and fourth 91 control signal conditioners and the inversion control block 92, as well as for resetting the D-flip-flop 84 to the initial state and for controlling, via the third switch, the error fixation block 79 and the second 89, third and 90 91 shaper control signals.

The control unit 87 of the third switch 88 provides switching of the switch 88 when transmitting signals from the inputs to the outputs. In the prototype device unit 87 is made on the P1TZ toggle switch.

The third switch 88 provides signal translation from inputs 114 and 115 to outputs 105, 117-119. The switching of the switch takes place when the potential at control input 113 changes from the control unit 87 to the third switch.

The second driver 89 of the control signals controls the operation of the third 95 and fourth 96 mode attribute generating units.

A third control signal driver 90 controls the operation of the fourth mode attribute generating unit 96.

The fourth control signal generator 91 generates the exchange synchronization feature (MBP) when the control device interacts with the memory unit.

The inversion control unit 92 generates an inversion feature for switching the third 76 and fourth 77 data inversion blocks in the data translation mode in the forward or reverse code when the memory blocks are monitored with the Read with Modification test

A third mode control unit 93 controls the operation of the second mode identification unit 94 when the mode of recording information in the memory block is changed from writing to words by writing.

The second block 94 of the formation of a mode flag forms a flag of recording information into the memory block with words or bytes (the CZP flag). The third mode forming unit 95 generates a read operation indication (PDT) when reading data from the memory block.

The fourth block 96 of the formation of the mode sign generates the sign of the operation of the Record of the TXTP when writing data to the memory block.

Transceiver control unit 97 controls the operation of transceiver unit 75 and transmitter unit 78.

A fifth feature generation unit 98 forms the mixed signal. A write-read (R / T) for synchronizing the operation of the error-fixing unit 79.

Write data bytes.

For operation in this mode, the controls are reset. The switching element of the error switching unit 80 is in the position of the NIS memory, which provides Log.1 at the output 106. The mechanically connected switching elements 139 and 140 (Fig. 10) in the second mode control unit 83 are set to the MMI position, forming at outputs 111 and 112 , respectively, the potentials of Log.1 and Log.O. The switching element in control block 87 of the third switch is set to Answer, setting potential 113 at output 113, allowing signals to pass from inputs X2 to outputs M of the multiplexer in switch 88. The inputs XI are locked. The switching element in the third mode control block 93 is in the position of the PPP (byte), while its output 125 will be the potential

Log.1. In this case, Log.1 will be sent to one of the inputs of the NE-132 element (see Fig. 7) in the block 79 for fixing errors on input 106, allowing the error signal (NIS ZU) to pass from the memory block to input 104

0 through the element AND-NOT 132 to one of the inputs of the element AND 131 and to the output 110-2. To the input 112 of the block 92 of the inversion control, a Log.O will arrive, setting the trigger 142 (see Fig. 15) through the AND element 141 and the trigger

5 143 to the state O, providing at their outputs nv respectively, at the inputs of the EXCLUSIVE OR 144 element and at the outputs 103, 124 of the Log.O. From the output 103 of the block 92 of the inversion control (figure 2) Log.O

0 is routed to the control inputs 103 of the third 76 and fourth 77 data inversion units, ensuring that data EXITS OR (Fig. 2, Fig. 5) passes from inputs 32 to outputs 99 through the elements EXCLUSIVE OR

5 block 76 and from the inputs 102 to the outputs 34 of the block 77 in the direct code.

The recording mode is set by the potential Log.1, which arrives from the output 29 of the feature formation unit 12 to the first inputs of the first and second formation units 94 and 95 of the mode indicator and the transceiver control unit 97. In this case, the element 2I-OR in the first block 94 of the formation (Fig. 16) is closed with the potential of 5 Log, 1 received at the inputs 29 and 125. The output 127 will have the signal Log.O with a duration equal to the duration of the signal Record at input 29, which corresponds to signal of the PPP on the timing diagram on

0 fig. 20 when writing data bytes.

The trigger circuits of the device are set to the initial state by the Reset signal received from output 49 of the first reset unit 8. This signal to the original

5, the state of the clock pulse generator 1, the first driver 2 of the control signals, the counter 3 addresses, the generator 16 pseudo-random code, block 22 comparison data, D-flip-flop 84,

0 second 89, third 90 and fourth 91 driver control signals. At the zero output 120 of the D-flip-flop 84 will be Log.1, at the outputs 121 and 122 of the second 89 and third 90 drivers of control signals

5, the Log.O will be set, and at the output 123 of the fourth driver 91, the control signals - Log.1. After the operator presses the Start button in the start block 24 in the first driver 2 from the output 27 (Fig. 1), a positive polarity pulse is generated, which is sent to the block 23, as well as to the D-flip-flop 84 (Fig. 2). ) and to the first input of the inversion control unit 92. Simultaneously, the output 31 of the second switch 6 (FIG. 1) receives the address code in the information transmitters block 78 (FIG. 2), and from the output 32 of the second data inversion block 20, the data code of the write information to the inputs 32 of the third data inversion block 76 . With the arrival of the circulation pulse on input 27 (Fig. 2), D-trigger 84 switches to state 1, and Log.O. turns on at its zero output, the negative difference of this signal will go to the first pulse distributor 85 and will propagate along the line delays inside the distributor 85, forming at the outputs 114 of the signal, delayed relative to the circulation pulse for different times. So, at the first exit 114-1, the delay will be 0.15 μs, on the second 114-2 - 0.25 μs, on the third 114-3 - 0.3 μs, on the fourth 1.14-4 - 0.45 μs, on p 114-5 - 0.5 μs, on the sixth 114-6 - 0.65 μs, on the seventh 114-7 - 0.7 μs, on the eighth 114-8 - 1.0 μs. From the third output 114-3 of the first distributor 85 pulses, a negative signal delayed by 0.3 µs will go to the second adjusting R input of the 0-flip-flop 84 and switch it to the O state. At the output 120 of the D-flip-flop 84 again it will become Log. one. Thus, at the output 120 of the D-flip-flop 84, a negative polarity signal with a duration of 0.3 µs is generated, which is fed to the input of the first pulse distributor 85. As a result, the outputs 114 of the distributor 85 will have negative polarity pulses with the indicated delays and a duration of 0.3 μs. From the output 120 of the D-flip-flop 84 a pulse (duration 0.3 μs) will go to the transceiver unit 75 and the information transmitter unit 78, turning off the transceiver unit 75 to the third state at the output and removing the ban on the operation of the information transmitter block 78, At this time, at the output 101 of the transceiver control unit 97 (Fig 2, 19), the signal Log.O which is sent to the third input 101 units 75 transceivers and switch It goes into data skip mode from inputs 99 to trunk 100. The address code from outputs 31 of the second switch 6 (Fig. 1) passes through the open transmitter block 78 (Fig. 2) and in the inverse code is sent to trunk 100 and then to memory block. After 0.15 μs, a negative pulse from the first output 114-1 of the pulse distributor 85 will go to the third input of the fourth driver 91 of the control signals (FIG. 11,

14), which will determine at its output 123 a MBP signal (exchange synchronization), which is sent to the memory unit, preparing it for operation, the Memory unit receives the address code from the trunk 100 and stores it in its register. After 0.3 μs, the negative pulse at the output 120 of the D-flip-flop 84 ends by turning off the transmitter unit 78 and turning on (removing the prohibition) the transceiver unit 75. Record data from the outputs 32 of the second data inversion unit 20 (Fig. 1) is transmitted in the forward code through the third data inversion unit 76 (Fig. 2), is fed to the inputs 99 of the transceiver unit 75, transmitted through it to the trunk 100 in the inverse code and then sent to a storage unit for recording reference information.

In the Recording mode, at the output 128 of the third block 95, forming the feature of the Log.1 mode, since Log.1 will go to input 29 and Log.O. will go to input 112. In this case, the output of the AND element 145 (Fig. 17) will be Log.1, the locking element NOT 146, which will cause Log.1 on the output 128. This means that when recording, the DChT signal (reading sign) is not generated.

In the recording mode, the output 129 of the device should receive the sign of the DZP in the memory block in accordance with the timing diagram (Fig. 20). The sign of the DZP is formed by the element 2I-OR-NOT (Fig. 18) in the fourth block 96 forming the mode sign. The input 112 of the second group AND elements 2I-OR-NOT of block 96 will receive a log. About from the second block 83 control modes and prohibit the passage of the signal from input 122. To the input 126 of the first group AND element 2I-OR-NOT Log.1 acts from the first the output 126 of the third block 95 of the formation of the mode indication, allowing the signal from the output 121 of the second driver 89 of the control signals to pass through the element 2I-OR-NOT. In the initial state, the output 121 of the driver 89 will be Log.O. From the output 114-2 of the pulse distributor 85, after 0.25 µs after switching on the D-flip-flop 84, a negative pulse will arrive and switch the D-flip-flop in the second driver 89 of the control signals (Fig. 14) to state 1, which will cause the signal Log.1 at output 121, which goes to the third input of the third unit 96 of the mode feature formation and, having passed through the element 2I-OR-NOT in it, appears at the output 129 in an inverse form, which means the beginning of the formation of the recording sign - DZP of negative polarity. Thus, in the memory block, the post / pili of the beginning of the DZP signals from the output of 129 and the MBP with

output 123. The memory unit, when it is healthy, reacts to these signals by issuing a response signal of a low-polarity low-voltage signal and sends it to the device input 116 (FIG. 2), which is sent to the input of the second pulse distributor 86 and to the fourth input of the switch 88 From the first output 115-1 of the pulse distributor 86, the delayed signal of the FCV enters the first (inverting) and second inputs of the group of inputs X2 (Fig. 13) of the switch 88 and passes through it to the outputs U1 and U2. From the output U2, the pulse delayed relative to the signal of the open conductor by 0.15 μs is transmitted (figure 2) to the second input 118 of the driver 89 of the control signals and switches the D-trigger in it to the position O with a positive front received from the output 118 of switch 88, causing the termination of the formation of the DZP signal in the fourth block 96 of the formation of the mode feature, i.e. the rear (positive) front of the DZ-P signal at the device output 129 is formed in 0.15 microseconds after the OT signal signal block appears at the device input 116. The DZP signal from the output 129 is sent to the memory block, and through the fifth block 98 of the formation of features of the modes - to the block 79 for fixing the errors. The signal from the input 116 enters the fourth input of the switch and (through it goes from output 105 to the second input of the error-fixing unit 79, where it (Fig.7) goes to the D input of the D-trigger 130, to the synchronous input C which will receive a signal from the output of the fourth block 98 of the formation of signs of modes. In this case, D-flip-flop 130 will record 1 at the zero output, which corresponds to the Sign of health, which in the form of Log.1 goes to output 110-1 and through element 131 to the output 109. From the output 110-1, the health sign is applied (FIG. 2) to the first input (FIG. 8) n and n display unit 81, as a result, the LED 133 is not lit, which indicates that the control device receives a signal from the control signal at the input 116 and that the memory unit is healthy in this sense. From output 109 (FIG. 2) Log.1 is sent to clock generator 1 impulses without prohibiting its operation. Autonomous monitoring systems are provided in the memory unit, which, in case of an error fixation, form a malfunction signal (NIS ZU) arriving at the control device input 104 and then to the inverting input of the AND-HE element 132 (FIG. 7) and from its output to output 110-2 of block 79 fixing errors and then to the second input of the display unit 81, lighting the corresponding error LED 134. In addition, the negative polarity error signal passes through AND 131 and is output from output 109 to the control input of the 1 clock pulse generator, stopping its operation. After

this, the operator proceeds to investigate the causes of the error signal of the NIS memory at the input 104 of the device. If the memory block, in response to the DZP and OBM signals received at its inputs from the outputs 129 and 123 of the control device, did not output the OTV signal to the device input 116, then from the output 105 of the switch 88 to the D input of the D flip-flop 130 (FIG .7) Log.1 will arrive, which will be recorded with the arrival of the clock signal at the input 108 in D-Trig5 ger. At its zero output, there will be a Log.O, which from output 110-1 reaches the anode of the LED 133 (Fig. 8) in the error indication block 81 and turns it on, which indicates the presence of an error in the memory block leading to the appearance of the signal OTV at its corresponding output. At the same time, the error signal in the form of Log.O. will pass (Fig. 7) through the AND element 131 of the block 79 to fix the errors and, from the output 109, go to the control

5 input 109 of the generator 1 clock pulses, slowing down his work. The operator then proceeds to clarify the reasons for the absence of the signal from the output of the memory unit. To verify the nature of the error

0 the operator using the button 135 in the error reset block 82 (FIG. 9) zeroed in the D-flip-flop 130 (FIG. 7) in the error-fixing block 79, removing the ban on the output 109 from the generator 109 from the clock generator 1

5 (figure 1). If the failure recurs, this indicates a persistent failure of the memory unit. For further troubleshooting by the absence of a signal from the memory unit in the monitoring device, a diagnostic mode with simulated signal from the monitoring device is provided. For this, the operator switches the switching element in the third control unit 87 to the OTV position. OTLK., Causing

5 input 113 of the switch 88 Log.O, which switches the switch 88 to the signal translation (Fig. 13) from inputs 1x1-4x1 to outputs U1-U4. In this case, the output 118 of the switch 88 by Wits signal received

0 to the 2x1 input (Fig. 13) from the distributor 85 and delayed by 0.65 µs (Fig. 11) with respect to the inversion pulse 27 on the C-flip-flop 84 C (the internal delays of the microcircuits are not considered). In this case, the window5 of the signal, Ј, ZP at the output 129 through 0.65 μs from the start of operation of the device (Fig.20). From the output 114-4 of the distributor 85 pulses, the signal delayed by 0.45 μs (FIG. 11) will go to the 4x1 input (FIG. 13) of the switch 88 and pass to its output 105, simulating

the presence of the signal OTV. which is sent to the second input of the error-fixing unit 79, where this signal will be received and recorded in the D-flip-flop 130. Thus, signals are received in the storage unit: in a period of 0-0.3 μs from the leading edge of the inversion pulse 27 the address code from transmitter unit 78 to trunk 100, and then write data to trunk 100 from the output of the transceivers. From output 123 - signal exchange rate (synchronization of exchange). From the output 127, the PZP signal is a sign of a byte recording and from the output 129 - DZP is a sign of the Record operation. The memory unit receives along trunk 100 first an address code, then a record data code, and responds to receiving information from the TO signals, which sends to the control device 116. After that, with the arrival of a new impulse to access the D-flip-flop 84, a new address code to the inputs 31 of the information transmitters block 78 and write data to the inputs 32 of the data inversion block 76, the process of writing information into the memory block will repeat.

Write data in words.

To write data in words (two bytes), the switching element in the third mode control block 93 is set to the position that provides at the output 125 Log.O, which is fed to the third input of the second mode indication unit 94. In this case, the Log.O (Fig. 16) goes to the inverting input of the first group AND element 2И-OR in block 94 and allows the negative polarity pulse to pass to the output 127 of the control device, which is a sign of writing data to the memory block. These words (and not bytes). In the time diagram (FIG. 20), the sign of the words is marked on line 127 with a note PPP. Otherwise, the principle of operation of the device does not differ from the work in the data recording mode bytes, described in the previous section.

Reading data from a memory block.

The indication of the read operation is the Log.O. coming from the output 29 of the operation characteristic formation unit 12 at the first inputs of the second 94 and third 95 formation units of the mode indicator.

In the read mode, the control unit generates and sends to the memory block (FIG. 2) the read mark of the subtle discharge detector at output 128, the sign of the PPP at output 127, the MBP signal at output 123, the code of the address to the trunk 100 in correspondence with the time diagram on Fig.20. The response signals are sent from the memory unit to the control device: a signal from the OTB to the input 116, a fault signal from the NIS memory to the input 104, the read data code from the trunk

100. The switching element in block 87 is set to Answer. From output 113 will be Log.1. The operation starts with the arrival of a signal Reset from the output 49 of the first reset unit 8 (Fig. 1). At the same time, the nodes and locks are reset, as in the recording mode. Log.O passes through the first input 29 of control transceiver unit 97 (Fig. 2), which locks the second group AND of element 2I-OR-NO in block 97 (Fig. 19), and the first group AND is closed by potential Log.O from input 112 In this case, the output 101 of the block 97 will be Log.1, which is sent to the third input of the transceiver unit 75 (FIG. 2) and switches it to the read data translation mode from the highway 100 to the output 102. Then, from the output 27 of the first driver 2 control signals (Fig. 1), a synchronous input C of the D-flip-flop 84 (Fig. 2) will receive an inversion pulse and switch it state 1. The negative front from the trigger 84 enters the input 120 of the first distributor 85 pulses and spreads along the delay line (FIG. 11) in the distributor 85. After 0.3 μs from the output 114-3 of the distributor 85 (FIG. 2) the negative front will hit the second R input of the trigger 84 and switch it to the O state. On the zero shoulder of the trigger 84, a negative pulse is generated, which propagates along the delay line of the user 85. From the output 120 of the trigger 84, the negative polarity goes to the control inputs 120 of the transceiver unit 75 78 and the block information transmitters. At this time, block 78 opens and the address code is transmitted from its input 31 to the output, and then to trunk 100 and then to the memory block. At this time, the transceiver unit 75 is closed and there will be a high resistance at its output 100. After the end of the negative pulse at the inputs 120 of the blocks 75 and 78, the transmitter block 78 is closed, and the transceiver block 75 is opened to transmit the read data from the magistral 100 to the outputs 102.

With a delay of 0.15 μs, a negative pulse from output 114-1 will go to the third input of driver control 91 and switch the D-flip-flop in it to the O position. With the signal coming from output 105 of the switch 88, the trigger in the driver 91 will switch to 1 and The output of the thermal driver 91 will generate an MBR signal in accordance with the timing diagram of FIG. 20, which is routed from the output 123 to the memory block.

On the first input 29 of the mode forming unit 95, the mode Log acts.

which passes through element AND 145 (FIG. 17), opens element HE 146 from output 126 of block 95, is directed to the fourth input of block 96, prohibiting the formation in it (FIG. 18) of a signal for recording hard-disk plates at the output 129 of the device.

With a delay of 0.25 μs, a negative pulse from the second output of the pulse distributor 85 (FIG. 11) is applied to the first input of the driver 89, the control signals, switches the O-trigger it (FIG. 14) to G, C output 121 a positive difference to the third input A second mode forming unit 95 and having passed through the HE element 146 appear as a negative front at the output of the block 95 and then from (Fig. 2) the output 128 of the device is sent to the block as a read character of the CTD. In addition, the synchronization signal of the exchange of MBP from the output 123 of the device will be received in the memory block. The OBM signal in the read mode is formed in the same way as in the write mode, therefore, when describing the read mode in detail, the process of generating the OBM signal in the driver 91 is not shown.

The memory unit, when it is healthy, reacts to the signals of the MBP 123 and the DCBT 128 by issuing a response signal from the TOV to the input 116 of the control device. The negative polarity signal from the input 116 is directed to the input of the pulse distributor 86 (FIG. 2) and to the fourth input of the switch 88. From the first output 115-1 of the pulse distributor 86, the delayed signal of the optical flux goes to the first (inverting) and second inputs of the input group X2 (Fig, 13) of the switch 88 and comes through it to the outputs of the U1. Y2. From the output U2, the pulse delayed negatively by the signal of the open conductor by 0.15 μs (figure 2) is fed to the second input 118 of the driver 89 of the control signals and switches the D-trigger in it (FIG. 14) to position O with a positive front coming from the output 118 switch 88. and will determine the end of the formation of the DChT signal in the third block 95 of the formation of the mode feature. Thus, the rear (positive) edge of the DChT signal at the output 128 of the monitoring device is formed within 0.15 microseconds after the appearance of the OTV signal signal storage unit at the device input 116. The PST signal from output 128 is sent to the memory block, and through the fourth block 98 of the formation of features of the modes - to the block 79 for fixing errors.

In the read mode, as in the write mode in block 79, the health of the memory block is monitored by two signs — the occurrence of a fault signal of the NIS memory on

the input 104 of the device and the presence of a signal of the open signal at the input 116 of the device. The presence of a NIS signal of negative polarity at the input 104 or the absence of a signal from the OTV

the input 116 after the output of the OBM signals at the output 123 and the PFS at the device output 128 indicates a malfunction of the memory block, which is fixed in the error-fixing block 79 and the output of the block 79 from the output 79 of the block 79 is sent to the control input of the 1 clock pulse generator (figure 1) and stops his work. The process of forming the stop signal 109 is described in detail in the description of the recording mode. For

5, the memory unit operation in the reading mode, in addition to the DChT and MBR signals, at the outputs 128 and 123 should also be generated the LTP signal at the output 127 of the device. The waveform of the PPP at the output 127 of the first block 94 to form the mode indicator depends on the position of the switching element in the mode control block 93. If the switching element is set to the -PZP position, then at its output 125 there will be a Log.G, which

5 is applied to the third input of the mode identifier formation block 94 and then (FIG. 16) is fed to the inverting input of the first group AND element 2I-OR and closes this group I. At one of the inputs of the second group

0 And a reading sign Log.O is received from output 29 (FIG. 1) of the operation sign forming unit 12, which allows (FIG. 16) the passage of a negative polarity pulse from the output of the D flip-flop 84

5 (FIG. 1) through element 2I-OR of block 94 in the inverse code to the output 127 of the device in accordance with the timing diagram (line 127) in FIG. If the switching element in block 93 is set to the Word position, then its output 125 will be Log.O. As a result, the first group I / I of element 2I-YLI in block 94 will be open and a negative polarity pulse will act on both inputs of each group

5 And, with one input straight and the other inverting. In this case, the function Va is realized, which corresponds to Log.1 at the output of block 94 and, accordingly, at the output 127 of the device. This does not contradict the requirements imposed on the LCP signal at the interface of the MPI.

The memory unit, having received from the control device in the first phase an address code from trunk 100 and from outputs 123, 127, 128, respectively, MBP, PPP and FFS signals, outputs to the highway 100 in the second phase data of the reading information, which are fed to the second group of inputs the outputs of the transceiver unit 75 and are transmitted through it at the output 102 and then through

the fourth data inversion unit 77 is directed to a group of inputs 34 of the data comparison unit 22 (Fig. 1). where the analysis of the information read from the memory block is performed by comparing it with the reference code. Based on the results of the analysis, it is decided to continue work in the case of equality of these codes or to stop in case of inequality. It should be noted that, in accordance with the requirement of the DIM, all signals entering the memory unit and back are formed in the reverse code, i.e. the presence of a signal is transmitted by a low level (zero potential). Therefore, transceiver unit 75 and transmitter unit 78 are made with inversion. In case of failure to receive the OTV signal from the memory unit (Fig. 2) at the input 116, the error-fixing unit 79 stops the operation of the monitoring device. In order to further diagnose the malfunction of the memory block, the switching element in the control block 87 of the switch 88 must be set to the OTV position. OFF, in which at its output 113 there will be a Log.O, switching switch 88 to the signal translation (FIG. 13) from inputs 1x1-4x1 to outputs U1-U4. In this case, the signal of the FCV is simulated by signals from the outputs of the pulse distributor 85. Further operation of the device during the internal simulation of the signal of the FCS is described in detail when describing the recording mode.

Reading with modification.

In this mode, in the first phase, the data from the memory block is read, information is analyzed, in the second phase, the new (inverse) information is written to the same address, and then the operation is repeated in the new address. Operation in this mode begins with a one-time recording with a stop, the mode of operation of which is given in the corresponding section of the description. The device is then switched to a cyclic read mode.

The resetting in this mode does not differ from the previous modes. The switching elements 139 and 140 in the second mode control unit 83 must first be set to the SET.MOD position. In this case, the output 111 of the block 83 will be Log.O (Fig. 10), and the output 112 - Log.1. From the output 111 of the block 83 Log. O, it is fed to the third input (FIG. 2) of the inversion control block 92, passes (FIG. 15) to the installation S input of the counting trigger 143 and through the And 141 element to the R input RS-trigger 142 , set trigger 143 to state 1, and trigger 142 - to O. From the trigger output 142, Log.1 goes to one of the inputs of the EXCLUSIVE

OR H4 and to output 124 and further to third bypass of transceiver control unit 47. Then, the switching device in the mode control unit 83 is switched to the MOD position. From the output 112 of the mode control unit 83, the Lo1.1 is fed to the fourth input of the inversion control unit 92, to the second input of the second mode indicator forming unit 95, to the first 0 input of the third mode characteristic forming unit 96 and to the second input of the transceiver control unit 97, preparing these blocks to work in the read mode with modification. From block 111 output

5 83 to the block 92 of the inversion control will go to Log.1, removing the setting potential of Log.O from the R-input of the trigger 141 (Fig. 15) and the S-input of the trigger 142. Shaper 91 of the control signals, the second block

0 94 formations and the third formation unit 95 of the mode feature generate 123, 128, 127 outputs at their outputs, respectively, the exchange rate synchronization signal, the PPM sign, the Record byte, and the read sign, 5 neither PDT in the first phase of the device operation, exactly the same as in the mode normal reading discussed in the previous section. From the output 124 of the block 92, the control of the inversion Log. O enters the third

0 input of transceiver control unit 97, generating at output 101 of Log.1, which is sent to the third (control) input of transceiver unit 75 and sets in it the data translation mode from trunk 100 to outputs 102. At the initial operation time from the first the reset unit 8 (FIG. 1) from the output 49 to the second input 49 of the inversion control unit 92 (FIG. 2) will receive a Reset signal which will switch

0 counting trigger 143 in lock 92 (Fig. 15) to the O position, which will determine at the output 103 of the block 92 Log.O. With the arrival of a return pulse to the input 27 of the D-flip-flop 84, a negative polarity of 0.3 µs is generated at its output 120, which is applied to the control inputs of the transceiver unit 75 and transmitter 78, closing the unit 75 and allowing the address code to be translated. from input 31 to outputs of block 78

0 transmitters and further to trunk 100 and then to the memory block. The memory unit responds to these signals by issuing a signal to the control device input 116, the presence of which is checked in the error-fixing unit 79.

5 After the memory unit receives the address code from the trunk 100 and OBM signals from output 123 and DCB from the device output 128 and outputs the signal OTV to the device inputs 116, the memory block outputs the read data 100 in the reverse code. By this time from

The output 120 of the D-flip-flop 84 negative ignition is completed and as a result, the transmitter unit 8 will close to the third state, and the transceiver unit 75 will open. The read data will pass from the trunk 100 through the transceiver unit 75 at its output 102 in the forward code and then through the fourth data inversion block 77 in the forward code to the inputs 34 (Fig. 1) of the data comparator 22, where the information is analyzed by comparing with the standard - Nymscode. If no errors were detected and the shutdown did not occur, then after the first basic operation of the device in the Read mode with a modification, the second phase occurs in which it is necessary to write to the memory block a return code to the same address from which the information was read. In this case, no repeated signal (Fig. 2) is output from the output 123 to the memory block. The control device must form the recording of the DZP recording at the output 129, receive the response signal of the OTV at the input 116 and Generate the CCD signal at the output 127 depending on the recording mode (bytes or words). At the end of the first phase of operation (reading the direct code), from the output 114-5 of the output group 85 of the distributor 85 pulses, the signal delayed by 0.5 µs relative to the circulation pulse at the input 27 of the D-flip-flop 84 will go to the fifth input of the inversion control unit 92 m and switch the trigger 142 (Fig.15) in it in 1. As a result, at the output 103 and 124 of the block 92 potentials Log.1. From output 103 of control unit 92, inversion Log.1 will go to the control input of data inversion unit 76, which will cause the recording data to pass from input 32 to output 99 in reverse to | ode. From the output 124 of the control unit 92, the control of the investment in Logic G goes to the third control transceiver block 97 and, having passed through the element 2I-ILY in It (Fig. 19) with the potential of the Logic O, will go to the third (control) input transceiver unit 75 and switches it to the signal translation mode from inputs 99 to trunk 100. From the output 117 of the switch 88, an impulse delayed in the distributor 86 by 0.15 µs relative to the signal of the OTV received at the input 116 of the device will be sent to the second installation control driver input 90 and switch D-flip ep in it (Fig. 14) in O. At exit 122 of shaper 90, a positive front passes through the fourth flea 96 forming a mode indicator to exit 129 and is sent to a memory block by a DGP recording attribute. The memory unit generates a response signal OTV to entrance

116 control devices The TV signal passes through the pulse distributor 86, then through the switch 88 and from its output 117 to the second installation input of the control signal generator 90, setting the D-flip-flop in it to the O state. At the output 122 of the driver 90, a negative edge of the positive signal that goes through the block

96 and will complete the formation of the sign of recording the DZP at the output 129 of the device and, accordingly, will result in the memory block issuing the response signal of the TOV to the input 116 of the control device. TSS response signal,

5, as in the previously discussed modes, is monitored by the error block 79. Simultaneously with the formation at the output 129 of the recording attribute of the CRC, the data from the inputs 99 of the transceiver unit 75 are passed

0 to line 100 and further to the memory block, where they are written to the same address from which information was read in the first phase of the work, but in the inverse code. Then on the D-trigger 84 synchronous input and the first input

5 27 the inversion control unit 92 receives the next inversion pulse, which will begin to form a new signal sequence on the D-flip-flop 84 and the pulse distributor 85, as well as

0 sets in O the trigger 142 (Fig. 15) in the inversion control block 92 and the process of reading the data in the first phase and writing the data in the inverse code is repeated, but at the next address of the memory block. This will continue until the complete enumeration of all the addresses of the memory block with the reading of the data and its analysis in the first phase and the recording of the inverse code data in the second phase in each of the addresses is completed. After

0 of this, from the first reset unit 8 (Fig. 1), the Reset signal will be sent to the second input 49 of the inversion control unit 92, which will pass to the counting input C of the counting trigger 143 (Fig. 15) and switch it to position 1. Then the whole process the operation will be repeated, but at the output 103 of the inversion control unit 92 the signal will be inverse with respect to the previously considered operation cycle of the device (where the cycle is the time

0 complete enumeration of all memory addresses) with the only difference that in the first phase of each clock cycle (where the clock-time control of one memory block address) reads the data in the inverse code with respect to

5 reading in the previous cycle. The data code in the inverse code from the output 102 of the transceiver unit 75 is supplied to the inputs of the fourth data inversion unit 77. At this time, the control input 103 of the block 77 will be Log.1, which will go to the control

the inputs of the elements EXCLUSIVE OR in block 77 (figure 5), which will determine the operation of the elements EXCLUSIVE OR as inverters. Consequently, at the outputs 34 of block 77, the data will go in the forward code. They are then sent to data comparison block 22 (Fig. 1) for analyzing the correctness of the information. In the second phase of each cycle of the second cycle of operation of the device, the input 114-5 of the inversion control unit 92 (FIG. 2) will receive a signal delayed by 0.5 µs relative to the inversion pulse received on the synchronous input C of the D-flip-flop 84, which will switch the trigger 141 in block 92 (FIG. 15) to position 1. This will determine the Log.O on the output 103 of the block 92. This signal will be sent to the control input of the data inversion unit 76, resulting in the block 76 passing the data from inputs 32 to outputs 99 to pr com code. Consequently, in the second cycle of operation, in the first phase of each clock cycle, data will be read from the memory block in the inverse code, followed by conversion in block 77 to the direct code, and in the second phase, data will be written to the memory block in the forward code (excluding inversion in block 75 transceivers). In the third cycle, the work is repeated as in the first, etc. In the Read with Modification mode, in case of blocking by a block 79, there is no TSP signal at the device input 116, the operator switches the device to the TFT signal imitation mode from internal signals and then performs diagnostics of memory unit faults.

The proposed device implements a new reading test with a modification that was not previously used in control equipment. This mode provides for reading data from a specific address and then writing other (inverse) information to this address and checking this information in the next monitoring cycle, which reveals the instability of the memory blocks that occur when working with computers. Ensuring the control of memory blocks with the MPI interface allows one to obtain a new quality, the technical and economic effect of which is expressed in reducing the costs of setting up both the memory blocks and the computing systems as a whole, which include the verifiable memory devices. At the same time, the area of use of the device is expanded, the reliability of the check of the memory blocks is increased.

Claims (1)

Claims of the Invention A device for monitoring RAM blocks according to author. No. 1265859, characterized in that, in order to expand areas of application of the device by tracing the liver of the possibility of monitoring memory blocks with a parallel interface, the information transceiver unit, the third and fourth data inversion unit, the information transmitter unit, the error fixing unit, the error turning off unit, the fifth display unit, the second second block 0 and the third block control modes, D-trigger, the first and second pulse distributors, the third switch, the control unit of the third switch, the second, third - and fourth drivers 5 control signals, an inversion control unit, a second, third, fourth and fifth units of the formation of a mode feature, a control unit for information transceivers, the first input of which is connected 0 with the first inputs of the second, third and fourth blocks of the formation of the mode feature, with one of the outputs of the formation block of the operation indication, with the control input of the second inversion block 5 and with the seventh input of the data comparison block, the output of the transceiver control transducer unit is connected to the first input of the transceiver unit of information, the inputs of the first group of which are connected to the outputs of the third data inversion unit, the inputs of which are connected to the information outputs of the device, the inputs of the second group of transceiver unit information connected to The 5 outputs of the information transmitter unit are the information inputs / outputs of the device, the outputs of the group of information transceiver blocks are connected to the inputs of the group of the fourth data evacuation unit, whose input is connected to the input of the third data inversion unit and the outputs of the fourth group data inversion unit connected to 5 information inputs of the device, the second input of the information transceiver unit is connected to the input of the information transmitter unit, to the input of the first pulse distributor, to the second input of the second mode characteristic forming unit and to the zero output of the D-flip-flop, the sync input of which is connected to the first input of the control unit inverters, with the first output of the first shaper 5 control signals and the input of the interrogation signal generator, the second input of the inversion control unit is connected to the first inputs of the second, third and fourth control signal drivers, with the first D-flip-flop setup input, with the third input of the generator, with the third output of the first reset unit, with the second input of the first control signal generator, with the reset input of the address counter and with the fourth input of the data comparison unit, the third input of the inversion control unit is connected to the first output of the second mode control unit, the second output which is connected to the second inputs of the third and fourth blocks of the formation of a mode feature, to the second input of the transceiver control unit and to the fourth input of the inversion control unit, the second output which is connected to the third input of the transceiver control unit, and the fifth input is connected to the fourth output from the output group of the first pulse distributor, the third output from the output group of which is connected to the second setup input of the D-flip-flop, the second output from the output group of the first pulse distributor is connected to the second input of the second driver of the control signals, and the first output from the group of outputs of the first pulse distributor is connected to the second input of the fourth driver of the control signals, whose third input is connected to the first output of the third switch and to the second input of the error fixing unit, the first input of which is the input signal of the device malfunction, the third input of the error fixing unit is connected to the output of the error shutdown unit, the fourth input is connected to the output of the second reset unit, fifth the input is connected to the output of the first block forming the mode indicator, the output of the error-fixing block is connected to the input of the generator, and the outputs of the group of the error-fixing block are connected to the pin the display unit, the outputs of the groups of the first and second pulse distributors are connected respectively to the inputs of the first and second groups of the third switch, the first input of which is connected to the output of the control unit by the third switch, and the second input is connected to the input of the second pulse distributor, second and third outs The third switch is connected respectively to the second input of the third and third input of the second driver control signals, the fourth output of the third switch is connected to the third input the third control signal generator, the output of which is connected to the fourth input of the fourth block forming the mode feature, the third input of which is connected to the output of the second the control signal generator and with the third input of the third block of the formation of the mode feature, the first output of which is connected to the fifth input of the fourth block of the formation of the mode sign, and the second output is connected to the first input of the fifth block forming the mode indicator and is the output of the device reading sign, the output of the fourth block forming the mode indicator is connected with the second input of the fifth block forming the mode and is the output the device recording feature, the output of the third mode control unit is connected to the third input of the second mode characteristic generating unit, the output of which is the output of the byte feature, device recording, the output of the fourth control signal generator is the device exchange output, D input of the D-flip-flop connected to the bus Log.1 device. $ 9 v 601AM Shch.g FIG 11 FIG. eleven /fe./J No.K / J (Reg. 19 012J45678901Z345678 FIG. 20