SU1608791A1 - Device for dividing pulse stream into recurring pulse trains - Google Patents

Abstract

The invention relates to a pulse technique and can be used in radio systems for dividing a stream of pulses consisting of an additive mixture of periodic sequences with a priori unknown periods into original sequences. The aim of the invention is to increase the speed of separation of the input pulse stream. The device contains AND elements 1, 7, 9, counters 2 and 4 pulses, strobe calculation block 3, strobe generator 6, counting block 8, pulse shaper 10, trigger 11, clock pulse generator 12, memory register 14. This goal is achieved through the introduction of counters 5 and 13 pulses, the arithmetic logic unit 15, blocks 16 and 17 of the RAM, control unit 18. 6 Il.

Description

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The invention relates to a pulse technique and can be used in radio systems for dividing a stream of pulses consisting of an additive mixture of periodic sequences with a priori unknown periods into initial sequences.

The purpose of the invention is to increase the speed of separation of the input pulse stream.

FIG. Figure 1 shows the electrical structure of the device; in fig. 2 is a structural electrical circuit of an arithmetic logic unit; in fig. 3 and 4 - structural electrical circuits of the RAM; in fig. 5 is a structural electrical circuit of the control unit; in fig. 6 - timing diagrams for the operation of the device.

The device (Fig. 1) contains the first element I 1, the first pulse counter 2, the strobe calculation unit 3, the second pulse counter 4, the third pulse counter 5, the gate generator 6, the second And 7 element, the counting unit 8, the third And 9 element, pulse generator 10, trigger 11, 12 clock pulse generator, fourth pulse counter 13, memory register 14, arithmetic logic unit 15, first 16 and second 17 random-access memory units, control unit 18. The first input element And 1 is connected to the input bus and the first input of the block 3, the second input with the inverse output of the generator 6, and the output with the write input of the counter 5 and the first input of the block 18, the first to the third outputs of which are connected respectively to the counting input of the counter 2 , with a subtracting input of the counter 5 and with the counting input of the counter 13.

Moreover, the output of counter 2 is connected to the second input of unit 3 and to the information input of counter 5, the output of which is connected to the third input of unit 3, the fourth input of which is connected to the output of counter 13, from the fifth to the seventh inputs - respectively from the fourth to the sixth outputs of block 18 and the output is connected to the input of the generator 6 and the S-input trigger 11, the R-input of which is connected to the second input of the unit 18, the output bus of the device, the reset input of the block 8 and the output of the And 7 element, the first input of which is connected to the direct output of the generator 6 and through shaper 10 with the first the input element And 9, and the second input - with the input bus.

The output of the trigger 11 is connected to the second input element And 9, the output of which is connected to the counting input of the block 8, the output of which is connected to the reset inputs of counters 2. 5 and 13. In block 3, the output of the generator 12 is connected to the counting input of the counter 4, the output of which is connected to information input register 14, the input of the last record is connected to the first input of block 3, and the output

-with the first input 19 of block 15, the second input 20 of which is connected to the first output 21 of the same block. The first information input 22 is connected to the output of the register 14. The second input 20 of the block 15 is connected to the second

information input 23 of block 16, the third input 24 with the output of block 16, and the second output 25 with the first address input 26 of block 17, the second address input 27 of which is connected to the output of counter 4, the first information input 28 to the output of block 17, output block 3 and with the first address input 29 of block 16, the second to fourth address inputs 30-32 of which are connected respectively to the second to fourth inputs of block 3, the first information input 22 - with the output of the register 14, and the fourth address input 32 - with the second information input 33.block 17. Block control inputs 16,17 and 15 are respectively connected to the fifth to lo: dmoy unit 3 inputs.

Element I 1 is intended to exclude from the analysis of the pulses of the input stream trapped in the exposed gate.

Counter 2 is designed to count the pulses of the input stream from 1 to I. Counter 5 is designed for reversing the counting of pulses from (1-1) to 1. Counter 4 is designed to count the time intervals TJJ, such that;

Tij ti -1,

where is the arrival time of the i-ro impulse of the input stream;

tj is the arrival time of the input stream j-ro and j (1, i-1).

The strobe calculating unit 3 is intended for calculating the moment of time vy-.

setting the gate and the formation of the sign

the impulse to belong to any sequence in the form of the number of the corresponding period

The generator 6 gates is designed to form a gate of duration d, the value of g is chosen based on the range

changes in measured periods and their measurement accuracy. Element And 7 is intended to test the hypothesis of whether the time interval Tij is a period of a pulse sequence entering the input stream or not.

The counting unit 8 is designed to count the number of pulses in the input stream, determine the moment of termination of the selected sequences and bring the selector to the initial position (reset from counters 2. 5 and 13). Element And 9 is designed to accommodate the passage of pulses from the output of the pho to the user of 10 pulses per counting input d of conversion unit 8, depending on the control signals generated on the trigger 11,

The shaper of 10 pulses is intended for the formation of pulses along the front of a front line. The trigger 11 is designed to generate a decision signal or prohibit the passage of pulses from the output of the driver 10 pulses to the counting input of the counting unit 8.

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Counter 4 is intended for calculating the mental time intervals and with the time counter in the selector. Pep 14 is designed to memorize pairs (the allelic code from the output of counter 14.

An arithmetic logic unit 15 is intended for calculating possible values of the periods and forecast times corresponding to the calculated periods. Api / fmetico-logic unit 15 (Fig. 2) consists of INPUT.X multiplexers 34 and 35, arithmetic logic element 36, memory register 37-39 and permanent memory 40), while the outputs multiplexers 34 and 35 are connected respectively to the first and second information inputs of the arithmetic logic element 36, the output of which is connected to the information inputs of registers 37 and 38,) d of the register 37 is connected to the first input input of the multiplexer 34, . the address input of the permanent memory (; the second block 40 is the output 21 ari () of the methico logical unit 15, the output of the register 38 is connected to the third information and || 1 input of the multiplexer 34 and the output 25 of the arithmetic logic 15 , the output of the permanent memory (unit 40 is connected to the information input of the register 39, the output of which is soy; | intact with the third information input of the multiplexer 35, the second inputs of the mulksor 34 and 35 are respectively the inputs 19 and 20 of the arithmetic logic The block input 24 of which is connected to the first input multiplexer 35.

arithmetic logic unit 15 operation-: as follows. The code of the time of the last pulse of the input stream is located in register 14 and arrives at 19 of the arithmetic logic unit 15. In | stroke 24 of the arithmetic logic block of block 16, the arrival time of the coming (L) -th pulse is applied. Through the mul

Typlexers 34 and 35, this information falls on the first and second information inputs of the arithmetic logic unit 36, respectively, which is transferred to subtraction mode by signals from 5 control unit 18. At the output of the arithmetic logic element 36, a difference code is generated.

Tij ti -1.

10 This value is rewritten into register 37, the output of which is connected with the first information input of the multiplexer 34 and with the address input of the permanent storage unit 40, in which the strobe value is stored equal to d II. This value is rewritten into register 39, the output of which is connected to the third information input of multiplexer 35. According to signals from control unit 18, multiplexers 34 and 20 35 are switched and the value TIJ is fed to the first information input of arithmetic logic element 36, and D 2 .

The arithmetic logic unit 36. operating in the subtraction mode generates a value (Tij - d / 2) at the output, which is then rewritten into register 37. From the output 21 of block 15, the value (Tu - d / 2) is input to the input 20 of block 15 and to the second information input of the multiplexer 35. After this, the signals from the control unit 18 control the arithmetic logic element 36 to the add mode, the multiplexer 34 again connects the ti to the first information input of the arithmetic logic element 36, and multiplexer 35 connects to the second information input el ment 36 value (Tjj - d / 2) luminant stored in register 37. Thus, at the output of the ALU element 36 is formed by a first prediction value:

tnp ti + TIJ - d / 2,

which is then rewritten into register 38. These calculations are carried out until the forecasts have been calculated for all periods, i.e. until the contents of counter 5 (storing the numbers of the previous pulses) become zero. In the case of a pulse entering the previously exposed strobe, the computations are performed according to the described algorithm m times. Calculations are based on recurrent formulas:

tnpi ti -i-Tij - (5/2:

 + Tij;

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tnp2 tnpl. , j, tnp3 tnp2 + Tij,

while during the calculation of this series of predictions, the value of Tij remains constant and is stored in register 37, and the forecast value tnp used in this calculation is stored in register 38 and after adding with Tij the new value of tnp is written to the same register.

Blocks 1b and 17 of the RAM are designed for storing, storing and issuing information, have the same internal structure (Fig. 3 and 4) and differ only in that in block 16 the address space is divided into two zones: the first zone is accessible through the inputs 30 and 31, and the second is at inputs 32 and 29. The first zone is equal to the counter width of counters 2 and 5 (since the counters of these counters are equal), and the second zone is equal to the counter width of 13. In block 17, the entire address space available at inputs 26 and 27. Consider the functional diagram of blocks op Operational memory on the example of block 16. It consists of input multiplexers 41 and 42 addresses, input data multiplexer 43, the outputs of which are connected to the corresponding address and information inputs of the operational storage element 41, the output of which is connected to the information input of the memory register 45. The multiplexers 41-43, the element 44, and the register 45 are controlled by control inputs connected to the corresponding outputs of the control unit 18.

The operation of blocks 16 and 17 of the RAM will be considered on the example of block 17. Inputs 26 and 27 of block 17 have the same size as counter 4 (Fig. 1). Through multiplexer 46, one of the address inputs is connected to the address input of the operative storage element 47, which also has the counter width 4. At the same time, input 26 in cell 47 selects the cell into which the information is recorded. After that, the signals from the control unit 18 (its operation is described to the address input of the operative storage element 47 through the multiplexer 46 connects the input 27 of the block 17, i.e. the outputs of the counter 4. When the contents of the counter 4 coincide with the address of the record, then from the corresponding cell of the block 17, the previously recorded information is read in. Thereafter, the information in this cell is deleted by writing zeros to this address.

The control unit 18 is designed to form the control diagrams of the operation of the selector; it can be constructed according to a known control circuit diagram with memory stored in memory. An example of the block diagram of such a block is shown in FIG. 5. The control unit 18 consists of a clock pulse generator 48, a pulse counter 49, a trigger, oa 50, an element OR 51,

a driver of 52 pulses, an AND 53 element, a pulse counter 54, a memory register 55, a permanent storage unit 56, a memory register 57. The counting input of the counter 5 is connected to the first input of the element OR 51 and is the first input of the control unit 18, the S input of the trigger 50 is connected to the second input of the element OR 51 and is the second input of the control unit 18. 10 The outputs of the counter 49 and the trigger 50 are connected to the information input of the register 55, whose recording input is connected to the output of the pulse generator 52, the input is connected to the output of element 15 OR 51, the counting input of counter 54 is connected to the output of element 53, the first input of which is connected to one of the control outputs of the register 57, and a second input connected to the output of the generator 48 and a recording input of the register 57, whose information input is connected to the output of the permanent storage unit 56, the address field of the latter is divided into two zones. The address inputs of the first zone are connected to the top of 25 counter 54, and the address inputs of the second zone are connected to the outputs of the register 55.; The reset inputs of the counters 49 and 54, the R-BXOs of the flip-flops 50 and 55 are connected to the control output of the register 57, the remaining 0 outputs of which are the control outputs of the control unit 18. The multiplexer 58 and the memory register 59 in the block 17 perform functions similar to the functions of the multiplexer 43 and the memory register 45 in the block 16, respectively.

Consider the algorithm of operation of the control unit 18. The trigger signals received at the first input of control unit 18 are fed to the counting input of counter 49 and 0, the first input of the element OR 51. The signal arriving at the second input of control unit 18 is stored in trigger 50 in the case of logical 1 and, moreover, to the second input of the element OR 51. The trigger signals from the output of the element 51 arrive at the shaper 52, which on the falling edge of the pulses arriving at it generates the pulses arriving at the input of the register entry 55 and re-recording the information from the counter 49 and the trigger 50 in reg Streit 55. codes output from the counter 54 and the register 55 are microinstruction location and provided to the address inputs of PROM 56 unit 5 (control memory). The counter 54 in the initial state has a logical O. therefore the code at the output of the register 55 is the initial address of the program corresponding to a certain algorithm of the selector operation.

The control signals from the output of the block go to the information inputs of Istra 57 (microcommand register) and, after recording, the output from the generator 48, are entered in register 57. If you need to perform several program steps, one of the control signals from the output of pel Istra 57 through the element And 53 transmits pulses from the generator 48 to the counting input of the gateway 54 and changes the code at its output, thereby the address of the microcommand selected from the block J6. The control signals of the outputs of register 57 control the operation of the devices 2, 5, 13, 15. 16 and 17 of the device (Fig.

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After testing the selected program n from the signals from the output of the register 57, the control block 18 returns to its initial state (dropping elements 49, 50, 54 and 55), after which the control block 18 is waiting for the next start signal on the first or the second entrances.

The operation of the device is illustrated by the timing diagrams shown in FIG. b (a-c), and consists in the implementation of the described algorithm.

In the initial state, the counters 2, 5 and 13 are reset to zero, and the counter 4 counts clock cycles from the generator 12. The counter 4 is not set and the initial state. Its width is chosen so that the maximum number that it can count, would be greater than the maximum period with which the proposed device operates, i.e., the counter size 4 is determined by the upper limit selectable (periods. In this case, when the situation when a larger number is subtracted from a smaller number, the introduction of one additional bit to reduce allows for the correct calculation of the period. To prevent this difference from affecting the other calculations, Yes, the loan signal is generated, which forms - when the deductible is less than the deductible. The preset input for the count- 4 is not needed, since when the bit is correct, the overflow 4 does not affect the correct operation of the arithmetic logic unit 15.

After the arrival of the first impulse (time — TI time, Fig. 6a) in register 14, fi-fier / time of its arrival, i.e. the binary code counted up to this point in time by counter 4. The contents of counter 2 are rewritten into counter 5. According to the signals from control unit 18, the contents of counter 2 are incremented by one, and at the address, formed. Oshusl. exit

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the counter 2, which is fed to the address input 30 of block 16, the arrival time (ti) of the input sequence pulse from the output of register 14 is rewritten by the information input 22 into block 16.

At the time (t2) of the arrival of the second pulse of the input stream, the register 14 again records the numeric code corresponding to the time of its arrival. This impulse

10 rewrites the contents of counter 2 into counter 5. After that, by signals from control unit 18, the contents of counters 2 and 13 are incremented by one, and the input thus generated

15 to 30 address block, information from the output of register 14 is rewritten from information input 22 to block 16. Thereafter, the time of arrival of the first pulse is subtracted from the address stored in counter 5 and received at address input 31 of block 16 Counter 5 stores the number of the previous (first) pulse of the input stream.

After that, the arrival time of the first pulse (ti) appears at the input 24 of the arithmetic logic unit 15, and the arrival time code of the second pulse (t.) Appears at the input 19. The signals from the control unit 18 at the output 21 of the arithmetic logic unit 15 form the value of the first estimated period Tr2

Tl2 t2 - ti,

which is fed to the input 20 of the arithmetic unit 15 and to the information input 23 of block 16. According to the signals from control block 18 and the period number stored in counter 13 and fed to address input 32 of block 16, the value of period Ti2 at input 23 is rewritten In block 16, and the output 25 of the arithmetic logic unit 15 generates a code for the estimated time (tnp) of the arrival of a pulse of the input stream (forecast time):

tnp t2 + Tl2- (5l2,

where d is the duration of the strobe generated by the generator 6 of the gates.

Since this time is calculated taking into account the correction by an amount equal to d / 2, a strobe is symmetrically set up relative to the expected arrival time of the input flow pulse. The numeric code corresponding to the forecast time from output 25 of arithmetic logic unit 15 goes to address input 26 of block 17. Data input 33 of block 17 is supplied with a period number code stored in 3 counters 13. Signals from control unit 18 are sent to block 17 at the tnp address, the number of the tested period Ti2 is recorded,

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then the control unit 18 connects the output of the counter 4 to the address input 27 of the block 17.

As soon as the contents of the score: ik 4 becomes equal to the calculated tnp value, the period number stored in block 17 at tnp appears at its output and starts the gates generator 6, which forms the strobe of duration d, i.e. gates generator 6 (FIG. 66) is started by a binary code of a period number different from zero. This can be done by the usual assembly of OR all bits of the number, and the resulting impulse to start the generator 6 of strobes. This gate from the generator output 6 gates is fed to the first input of the element And 7, and from the inverted output of the generator 6 gates, the signal is fed to the second input of the first element And 1, thereby blocking the passage of input pulses to the input of the counter 5. To the second input of the element And 7 and to the first input of the element I 1 pulses of the input stream are applied. Thus, during the formation of the strobe, the passage of a pulse to the input of the selector is prohibited and the passage to the exit is allowed.

According to the signal at the output of the device (Fig. Bv) and, therefore, trapped in the strobe, the control block 18 generates signals of the tracking algorithm, which is used to perform the following operations / By the number stored at the output of the block 17 and arriving at the address input 29 of block 16, the value of the period Ti2 (estimated) is read from the latter and is fed to the input 24 of the arithmetic logic unit 15. At the input 21 of block 15 there is the time of arrival of the last pulse Tc. The signals of the control unit 18 at the output 25 of the arithmetic logic unit 15 form m prediction times for a given period Ti2 (for example, m 3): t3 + Tp-612;

tnp2 tnp1 + ti2; tnp3 tnp2 + ti2.

The number m is selected as follows. It must be greater than 1 in order to ensure stable tracking of the sequence in case of gaps in it. On the other hand, the number m should not exceed (much more than that) the minimum necessary for making a decision about a stable sequence. The number m 3 was taken as the outcome of the probabilistic characteristics of the streams with which it was intended to handle this device. They were most likely to have single gaps, and for a sustained escort of the ped. At least one hit in the gate exhibited for neo is sufficient.

Thus, at the moment when the contents of counter 4 coincide with the values

tnpi, tnp2, tnp3 ,, gates are formed by the described method for a sequence with a period of Ti2.

If during the formation of the strobe at the output of the strobe generator 6, the input flow pulse does not enter the selector input, which is possible if it does not belong to a sequence with a period of Ti2, or if the time interval Ti2 is not the period of any input flow sequence, then the period determination process continues. An input stream pulse that did not hit the gate records in register 14 the state of counter 4 and rewrites the contents of counter 2 into counter 5.

0 Thereafter, the control unit 18 generates signals by which the state of the counters 2 and 13 is increased by one, the code stored in the counter 2 is connected via address input 30 to the address bus of the block 16. By

5, information input 2 in block 16 records the state of register 14, i.e. arrival time (ts) of the input stream pulse. After that, the control unit 18 connects to the address input 31 of the block 16 the counter output

0 5 and at the address stored in this counter, from block 16, the arrival time of the previous pulse (t2) is read, which is fed to the input 24 of the arithmetic logic unit 15, at the input 19 of which there is a code.

5 (t3). The signals from the control unit 18 at the output 21 of the arithmetic logic unit 15 form the value of the second estimated period T23 (in counter 13, it corresponds to code 2)

0T23 t3 - 12:

which is fed to information input 23 of block 16. According to the signals from control block 18 and the period number stored in counter 13, the value of period T is recorded by input 23 to block 16, and output 25 of the arithmetic logic unit 15 a code is calculated for the expected time of arrival of the pulse (forecast time) for the time interval T2z:

0Хпр ТЗ + Т23 - д / 2.

The numeric code corresponding to the forecast time from the output 25 of the arithmetic logic unit 15 is fed to the address input 22 of the block 16, and at this address in the block 16

5, a new value of the period number from the counter 13 is recorded.

After this, the value of the counter 13 is increased by one, and the value of the counter 5 is reduced by one. Thus, in number 5, the number of the first pulse arriving at the input of the selector is formed. According to this (the value of counter 5 from block 16 of the time of arrival of the first pulse is fed to input 24 of the arithmetic of logic block 15, at input 19 of which there is a time of arrival of the last | pulse of the input stream (r3): 21 of the arithmetic logic unit 15 - the value of the third hypothetical period Ti3 (in counter 13 it corresponds to (code 3) |

Tl3 t3 - t,

KOTcjpoe according to the corresponding number of the perimeter in counter 13, is recorded at data input 23 in block 16. At this input 20 of arithmetic logic 15, is the value of the estimated period Ti3, and the signals from block 18 at the output 25 of arithmetic the logic block 15 generates the code of the impulse arrival time of the pulse tt lT1z- (5/2. The numeric code corresponding to the time of tnp prediction, from the output 25 of the arithmetic logologist eccoro of the block 15 is fed to the address 26 of block 17 and at this address it starts from the counter 13 the number of the new-, third-year period for which d this forecast.

Thus, when the content of count 4 becomes equal to the values of tnp tnp, the generator 6 of gates will put forward to test the hypothesis of whether the proposed T2c or Ti3 periods were 2 and 3) sequential-input periods. The algorithm of the selector in the case of impulses entering the set gates is considered (ti). This is a tick) porjo

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In the event of the termination of the arrival of pulse sequences at the input, the device is restored to the initial state. For this purpose, serve blocks 8-11 1). The signal that triggers the generator 6 08. sets the state of 1 trigger 11., which allows the pulse from the output of the imaging unit to 10 pulses through the element; the even input of the counting unit 8. On the output of the imaging generator 10 - - - on the rear the front of the strobe, because of the occurrence of signals at the exit of the pore, is set to a logical O flip-flop 11 (I close- and the E 9) and reset the reset 3 3. If the signals at the selector's output appear, then the pulses from the output of the - worlds, ztel 10 pulses through the open element 4 and 9 od m to the count input pen

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the counting unit 8, fixing in it the number of gaps going to the row. If this number exceeds the specified number, a signal appears at the output of block 8, which sets the device to its initial state. The number of passes is determined by the maximum number of sequences that make up the input stream and is chosen to be equal to the number of sequences multiplied by the number m (in our case m 3).

A feature of this selector is. that the testing of all possible hypotheses is carried out by impulse, i.e. for each 1st pulse, a time interval is considered (1-1), however, the total number of time intervals counted and prepared for the test, to a given point in time, is carried out using the well-known combinatorial formula:

WITH

2 (I - 2) and makes up a complete group of events.

The time it takes for the input stream to split into source sequences depends on the periods of these sequences. So. for example, for an input stream consisting of sequences with periods T 40 T 620. T 1400 and T 3500 μs. the separation time of all four sequences is 10.5 µs. after which the selector begins to consistently accompany these sequences. The known device separates a similar input stream in a time of about 400 ms (assuming a Cmin 40 µs and A T 10 µs).

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Claims (1)

Apparatus of the Invention A device for dividing a pulse flow into periodic pulse sequences comprising a first element I, a first pulse counter, a strobe calculator, the output of which is connected to the S input of a trigger and the input of a generator of strobes which output is connected to the first input of the second element I and through the pulse driver with the first input of the third element I. whose second input is connected to the trigger output, the R input of which is connected to the reset input of the per-meter unit, to the output bus and the output of the second Element I. whose second input is connected to the input bus, the strobe calculating unit contains a clock pulse generator, a second pulse counter and a memory register, whose recording input is connected to the first strobe calculating block input, characterized in that. what. In order to increase the separation speed of the input pulse flow, a third pulse counter, reversible, the fourth pulse counter and a control unit, the first input of which is connected to the recording input of the third pulse counter and the output of the first element And whose first input is connected to the input bus and the first input of the strobe calculator, the second input of which is connected to the output of the first pulse counter and the information input of the third pulse counter, the third input - to the output of the third counter ka pulses, the fourth input with the output of the fourth pulse counter, and the reset inputs of the first, third and fourth pulse counters are connected to the output of the counting unit, the counting input of which is connected to the output of the third element And, the counting input of the first pulse counter, subtracting the input of the third pulse counter and the counting input of the fourth pulse counter is connected respectively to the first to third outputs of the control unit, the fourth to the sixth outputs of which are connected respectively to the fifth through seventh inputs the strobe calculating unit, and the second input - with the output of the second element I, the inverse output .. of the strobe generator being connected to the second input of the first element I, and the first and second memory blocks and the arithmetic logic unit, the first input which is connected to the output of the register m m ty and the first information input of the first memory block, the second input with its the first output and the second information input of the first memory block; the third input is with the output of the first RAM block, and the second output is with the first address input of the second block memory, the second address input of which is connected to the output of the second pulse counter and information input of the memory register, the output to the output of the strobe calculator, to the first information inputs of the second memory block and to the first address input of the first memory block, The second to fourth address inputs of which are connected by the corresponding second to fourth inputs of the strobe calculator; the fourth address input of the first random access memory block is connected to the second information input v one block of RAM, and the control the inputs of the first and second RAM blocks and the arithmetic logic unit are connected respectively to the fifth through seventh inputs of the strobe calculator, and the output of the clock generator is connected to the counting input of the second pulse counter. Y7 / g iSjrod R g: L. J Exercise ola 1 I  T