SU1485265A1 - Queueing system simulator - Google Patents

Description

The invention relates to the field of computing. Purpose of the invention2

* Niya - expanding the functionality of the device by simulating the mode of group receipt of applications in the queue for maintenance. The device contains a shift unit, a clock generator, a reversible counter, a polling unit, an output unit, a controlled request generator, a service enable signal generator, a block of bar elements, an interrupt unit, a packetization unit. The device allows you to simulate the work of queuing systems with queues with group discipline of requests to the queue and service interruptions at the time of receipt of applications in the queue. 4 il.

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The invention relates to computing and can be used to simulate processes in queuing systems (QS).

The aim of the invention is to expand the functionality of the device due to the simulation of the mode of group receipt of applications in the queue for service.

FIG. 1 shows a block diagram of the device; in fig. 2 - diagram of the shift block; in fig. 3 is a blocking unit diagram; in fig. 4 - block diagram interrupt.

The device (Fig. 1) contains a shift unit 1, a generator of 2 pulse cycles, a reversible counter 3, a polling block 4, a pre-entry input 5, a controlled generator 6 of applications, a generator of 7 service enable signals, a prohibition block 8, an interrupt block 9, a block 10 palletizing, launch input 11 and setup input 12.

Block 1 shift is a non-standard version of the shift register.

Shift register 1 consists of a priority discharge blanking unit 13, a bi-directional shift register 14 with sequential and parallel insertion, a priority discharge determining unit 15 and a NOT element 16. Register 14 has serial input inputs сд + when shifted to the right, clock counter input C, control inputs Ει and Ез to select the mode of operation, input /? - installation

Depending on the state of the setup inputs Ει, Ег and Ц, the register can operate in various modes: sequential insertion with a shift to the right; sequential entry with a shift to the left; parallel entry; storage; set to "0".

In the sequential-entry mode with a shift of information to the right, to the input E, the logical level “0” is applied, to the input Еg - the logical level “1”. Parallel recording of information is carried out when the installation inputs are in a logical "1" state.

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The priority discharge blanking unit 13 contains delay elements 17 and blanking circuits 18.

The structure of the shift block includes the elements OR 19, the elements AND 20 and 21, the elements NOT 22, the elements AND 23, the elements OR 24, the elements NOT 25 and the elements AND 26.

The functional purpose of the inputs and outputs' of the shift unit 1 is the following: input of clock pulses from generator 2 (input C of the standard shift register); inputs for receiving polling signals from polling unit 4; input of bids from the packetizing unit (input Ώ + standard shift register); the output signal of the absence of applications in the queue (the output of the element is NOT 16); the output of applications submitted for service (the output of the element OR 19); the output of applications received for service, but due to the presence of a queue of requests or the absence of a signal that the service has been completed for a previously received application that have been queued for service (exit shift register discharge Ι-γο); the output signal of exceeding the fixed time limit of the application in the queue, i.e., this output removes requests from the queue, due to the fact that their waiting time for service has exceeded the limit value (output of the last digit of the standard shift register).

The packetization unit 10 (FIG. 3) is designed to ensure the operation of the device in the mode of group receipt of requests in the service queue and contains the first 27 and second 28 elements And, the trigger 29, the sensor 30, the first 31 and the second 32 reversing counters, the first 33 and second 34 elements OR, exit 35.

Counter 31 is used to combine the applications in the group. The number of applications collected in the group is equal to the binary number recorded from the code sensor in the reversible counter.

The counter 32 is used to count the number of clock pulses required for sequential queuing of a block of a shift group of requests.

The trigger 29 is used to control the queuing of the block shift groups of applications.

Sensor code 30 in the simplest case can be a group of keys, depending on the position of which at the outputs of the code sensor there can be a logic level “0” or a logic “1”.

Interrupt block 9 (Fig. 4) is designed to ensure the operation of the device in the service interruption mode of requests and contains an AND-HE element 36, a delay element 37, a reversible counter 38, an OR element 39, a NO element 40, an OR element 41, an AND element 42, the reversible counter 43, the element OR 44, the element And 45, the switch 46, the element And 47, the trigger 48 and the sensor 49 code.

Reversible counter 38 is designed to count the number of non-processed interrupts, counter 43 - to set the time for one interrupt.

The sensor 49 of the code in the simplest case may be a group of keys, depending on the position of which at the outputs of the code sensor there may be a logic level "0" or a logic level "1".

The device works as follows.

When simulating open SMO from the installation input 12 of the device to the input of the block 8 of the elements of the prohibition receives a signal prohibiting the passage from the discharge outputs of the reversible counter 3 to the input of the control frequency of the generator start 6 applications.

When simulating closed QS, the passage of signals from the bit outputs of the reversible counter 3 to the input of the generator start frequency control of 6 applications is permitted.

With the output of the generator 6 applications receives a stream of pulses that simulate the flow of applications in the QS. The intensity of this flow in the process of modeling open QS remains constant. In the simulation of closed QS, the intensity of the flow of pulses varies depending on the number of applications.

Information on the number of orders currently in the system is stored in the reversible counter 3.

On the basis of the information stored in the reversible counter 3 and coming through the block of elements of the prohibition on the input of the frequency control of the generator 6, it is configured.

When simulating open and closed QS without interrupting service applications, the switch 46 of the block 9 interrupt is in position I. The level of the logical unit is fed to the second input of the element 45 of the block interrupt. The item is open. The pulses from the generator 2 are received at block 7 of the formation of the signals of the resolution of service.

When simulating open and closed QS with the interruption of service applications, the switch 46 of block 9 interrupt is in position. The trigger 48 controls the flow of pulses from the generator 2 to the block 7 of the formation of the signals allow service.

Before starting work in this mode, a binary number is entered on the code sensor 49, which specifies the amount of time for one interrupt. At the input 5 of the pre-recording of information, an impulse is given, by the decay of which the binary information from the sensor 49 of the code is written to the counter 43, the front of the im5

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pulse delayed by the delay element 37 at the response time of the counter 43, the element OR 44 and the counter 38, the latter is reset. In the future, at input 5, the level of logic zero is maintained. At the outputs of the counter 38 and the element OR 39, the logic level is zero, the level of the logical unit is supplied to the single input of the trigger 48 from the output of the element OR — NOT 39. The trigger in a single state. The clock pulses from the generator 2 are passed to the block 7 of the formation of the signals allow service.

When modeling open and closed QS with interruption of service of requests in the mode of single receipt of requests in the service queue, the binary code “0001” is set on sensor 30 of the packetizing unit code 10, which corresponds to one, i.e. the number of applications reported to the group is equal to one .

When modeling open and closed QS with interruption of service of applications in the mode of group receipt of applications in the service queue, a binary code equal to the number of grouped applications is set on the code sensor 30.

Before starting work in this mode, the trigger of the packetizing unit 10 (FIG. 7) must be set to the zero state; a binary number must be written to the counters 31 and 32 from the sensor code 30, specifying the number of applications collected in the group (for example, K).

The operation of the device begins with the fact that the starting input 11 comes a stream of pulses simulating the end of the maintenance of the next application and the possibility of starting the next service. This signal is stored in the imaging unit 7. An impulse of the application to the input of the packaging unit 10 is also issued. On a positive differential clock pulse from the generator 2 (it simulates the current time) the application pulse passes the element And 27 and enters the subtracting input of the counter 37, reducing its content by one. When it becomes zero (this means that a group of K applications is formed), from the output of the element OR 33 to the input of block 9 interrupt, an interrupt signal is sent in the form of a negative potential difference. Also, this signal is sent to the synchronization input of the counter 31 and, from its information inputs from the sensor 30, a binary number is again recorded indicating the number of applications to be grouped - K. The counter 31 is ready to receive the next group of applications. At the same time, the interrupt pulse sets the trigger 29 to one state. A positive potential is supplied to the input ϋ of the I shift block, by which units (requests) will be written to the shift register, which simulates the service queue, with each clock pulse. Through K clock pulses in the shift register of block 1 will be written To applications, and the counter 32 of the packaging unit 10 will reset and the negative potential drop from the output of the element OR 34 sets the trigger 29 to the zero state.

The submission of applications to the service queue will cease until the next group of applications for K pieces is formed again. And the group of applications has one interruption.

By a positive clock pulse difference from generator 2, the end-of-service signal of the next application, which was stored in shaper 7, is fed to reversible counter 3. Simultaneously, the same signal is triggered by polling unit 4, which provides a level to the input of the standard shift register (Fig. 2) logical zero, and from the information outputs - polling signals (logical "1"),

In the presence of an interrupt signal from the packetization unit 10, a unit is recorded in the reversing counter 38 of the interrupt block by a positive clock pulse difference from the generator 2. The trigger 48 is in a single state, the element And 45 is open, the clock pulses from block 2 pass to block 7.

If there is an application pulse from the packetization unit 10, a positive offset of the clock pulse from the shift register generator 2 (FIG. 2) is followed by a sequential entry mode “1” with a shift to the right, and binary information in the parallel code is sent to the node 15 to determine the priority discharge standard shift register (this will be the first in order, starting with the most significant digit containing the logical unit).

From the established priority discharge, an impulse (application) through the element OR 19 is issued for servicing. Thus, the service with the longest waiting time is selected for service (the discipline “First come - first served”). Also, the pulses come respectively from the first low-order digit of the standard register to the reversing counter 3 and from the output of the element NOT 16 to the block 7 of formation.

After servicing the application for triggering input 11, a signal is received, imitating the possibility of starting service of the next application, which sets the formation unit to one state, and the trigger 48 of the interrupt unit is in the zero state. Element And 45 is closed, the arrival of the clock pulses on block 7 termination 7

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It appears that the service permission signal of the next request for the polling unit is not received. The input element And 42 with the inverse output of the trigger 48 receives the logical level of "1", the clock pulses write off the contents of the counter 43.

When the contents of counter 43 become zero, the negative potential drop at the output of the element OR 44 is fed to the subtracting input of counter 38, reducing its content by one, as well as to the synchronization input of counter 43 and, using its bit inputs, a binary number is written from the code sensor interruption time.

Thus, the time of one interruption will be

T2 = L ‘> (,

where is the time of one interruption;

Ζ? 2 - a binary number supplied from the sensor code to the inputs of the counter 43;

(- period of clock pulses supplied from the generator 2 to the subtracting input of the counter 43.

If, during the service time of the current request, the system received several requests or interrupt signals (for packaging mode), the service time of the current request is increased by the total time of interruption from all incoming requests or interrupt signals as follows.

When writing the number to the counter 43 from the sensor 49 of the code at the output of the element OR 44, a logical “1” appears, which through the element OR 41 enters the synchronization input from the counter 43.

The process of writing off information resumes, and so on, until the contents of the counter 38 reaches zero, which means the end of the interrupts. At the output of the element OR — NOT 40, a level of logical units appears. The trigger 48 goes into one state and the passage of clock pulses to block 7 is resumed. Signal permission service next application enters the polling unit.

Thus, the interrupt block provides an increase in the service time of the current request for the time of interruption.

After polling, block 4 supplies the input V) of the standard register (FIG. 2) with the level of a logical unit (the logical level “1” is constantly maintained at the input Er).

At node 13 of shift register 1, the following occurs.

The inputs 1–8 of node 3 receive, respectively, binary information from the outputs of register 14 and the outputs of node 15. As a result of the operation of the elements of node X, the inputs of the standard register 14 in parallel input mode enter information in all bits without change except for the priority digit, in which the logical the unit is reset, i.e. it is extinguished.

If at the moment of polling the shift register 1 is empty, a signal about this goes through the element NOT 16 to the driver 7 in order to repeat the poll in the next cycle. If there is a positive difference in the clock pulse, this signal passes through the output of the device and simultaneously starts the polling unit 4.

Thus, in the course of device operation, the reversing counter 3 is constantly fed pulses: to the summing input — from the lower digit of the standard shift register (the number of applications received for service), to the subtracting input — from the former 7 (number of applications served). Therefore, at any time in the reverse counter 3 contains information on the number of applications in the system.

The device allows you to simulate the operation of closed and open QS with interruption or without interruption of service requests in the mode of single or group receipt of applications for the queue for service.

Claims (1)

Claim A device for simulating queuing systems containing a shift unit, a clock pulse generator, a controlled order generator, a reversible counter, an interdiction block, a polling block, an interrupt block, a service resolution driver, the information input of which is connected to the no-call alarm output in the block queue shift, the clock input of which is connected to the first output of the clock pulse generator, the shift control input and the group of information inputs of the shift block are connected to the output Dami polling unit, information input of which is connected to the first output of the polling permission resolution of the driver of the service enable signals, the output of the service exit of which is connected to the subtractive input of the reversible counter and is the output of the service end of the device application, the output of the first digit of the shift unit is and connected to the summing input of the reversible counter, the bit outputs of which are connected respectively to the information inputs of the element comrade query, managing the input of which is the input setting rezhi1485265 ten the device’s operation, and the outputs of the prohibition block are connected respectively to the control inputs of the request generator, the output of the last digit of the shift block is the output of requests excluded from the device queue, the input to the device start is the start input of the interrupt block and the service permission shaper, the output of the request for no requests the queue of which is the output of the absence of requests in the device queue, the information output of the shift unit is the output of the application for service The clock input of the service resolution driver is connected to the information input of the interrupt unit, the pre-recording input of which is the pre-recording information of the device, and the clock input is connected to the second output of the clock generator, characterized in that the account of the simulation of the mode of group receipt of applications in the service queue, it additionally contains a packetization block consisting of two x reversible counters, two elements OR, code sensor, trigger and two elements AND, the first input of the first element AND is connected to the output of the controlled generator of requests, the second the input is connected to the third output of the clock pulse generator and the first input of the second element. And the output is connected to the subtractive input of the first reversing counter, the summing input of which is connected to the potential potential bus, the discharge inputs of the first reversible counter are connected to the corresponding outputs of the code sensor and the discharge 10 the inputs of the second reversible counter, and the installation input of the first reversible counter is connected to the zero potential bus, and the discharge outputs are connected to the corresponding inputs of the transducer Vågå OR gate, the output of which 15 is connected to the input of the receipt of requests of the interrupt unit, the synchronization input of the first reversible counter and the single trigger input, the zero input of which is connected to the output of the second OR element and the synchronization input of the second reversible counter, and the direct output of the trigger block and the second input of the second element And, the output of which is connected to the subtractive input of the second reversible counter, the summing input of which is connected to the single potential bus, the installation input of the second reversible account snip is connected to zero potential bus and the bit outputs are connected to respective inputs of a second OR gate. fzg.1 1485265 To block 3 Phi 2 From the generator ^ t-1 ^ From the general 27 thirty G * G 28 > with > * 7 Р1 Ώ2 2Н Ζ »ME 31 G * 3 <block9 > & t [l / $ ers8ani <1 (K-H £ 36) 8 block 1 sd8igo! Oh ^ 35 32 ^one I* 39 Fig.Z 1485265