SU1541612A1 - Device for registering unstable failures - Google Patents

Abstract

The invention relates to the field of computer technology and can be used for fixing unstable failures in the process of cyclic operation of digital objects of study. The purpose of the invention is to increase the reliability of fixing unstable failures. This goal is achieved in that the device containing the first 1 and second 12 elements is AND, the first 2 and second 10 registers, the first 3, the second 4 and the third 5 counters, the OR-NOT 6 element, the first 7 and second 8 comparison blocks, the element OR 16, the first trigger 18 and the display unit 15, the third register 9, the third element AND 11, the third comparison unit 13, the NOT element 14, the second 17 and the third 19 trigger with the corresponding connections are entered. Returning to the control of the first element of the sequence after controlling the last element allows, in contrast to the prototype, to exclude "idle" cycles (i.e. cycles, at which control does not occur) while controlling sequences having length L less than maximum 2 ^N -1, where N - the size of the second counter 4, which leads to an increase in the frequency of control of each element. 2 Il.

Description

The invention relates to computing.

The purpose of the invention is to increase the reliability of fixation of unstable failures,

FIG. 1 shows a block diagram of the device; in fig. 2 is a timing diagram of control cycle control.

The device contains the first element AND 1, the first register 2, the first 3, the second 4 and the third 5 counters, the element OR-NOT 6, the blocks 7 and 8 of the comparison, the registers 9 and 10, the elements of the 11 and 12, the third block 13 of the comparison, element NOT LU, display unit 15, element OR 16, triggers 17-19, information input 20, clock input 21, control cycle start output 22, initial setting input 23 and output 24 fail, i

The device works as follows.

The input 23 of the initial installation of the device receives a signal on which the second 4 and third 5 counters, the second register 10 and the second trigger 17 are reset to the zero state, the first counter 3 and the third register 9 enter the unit codes for all bits, and the first trigger 18 is set to one. A zero value at the forward output of the second trigger 17 keeps the third trigger 19 in the zero state.

The output 22 of the start of the cycle control-1 l receives a signal oi, indicating the beginning of the next control cycle. In each control cycle, a controlled sequence of M-bit information elements with a reproducible length is controlled by the object using the same algorithm. The monitored information is fed to the inputs of the first register 2 and the first comparison unit 7. The maximum duration of the monitoring cycle is determined by the difference of the third counter 5, the counting input of which, being the clock input of the monitored element 21, receives the synchronization signals, by which the elements of the monitored sequence arrive. In this case, the number of the next element is determined at the information outputs of the counter 5. The number of cycles of control of each information element is determined by the difference of the first

counter 3, to the counting input of which, through the first element I 1, signals start of the next control cycle. At the information outputs of the first counter 3, the number of the current control cycle is determined.

After completion of all control cycles of one information element with the arrival of the next signal about the output of the transfer of the first counter 3, the front is generated, increasing by one the code at the information outputs of the second counter 4. This code indicates the number of the element under study. The bit width of the second meter 4 is equal to the bit width of the third meter 5, which makes it possible for the numbers of all information elements to appear at the outputs of the second meter 4.

The codes from the information outputs of the second 4 and third 5 counters are fed to the inputs of the second comparison unit 8, which, when the codes match once, generates at the output of the equality of the compared codes a single value. This single value through the second element And 12 is fed to the synchronization input of the first register 2, allowing reception of the element of controlled information on the first control cycle, and through the third element 11 - to the synchronizing input of the second register 10, allowing reception of the comparison result from the output of the first comparison unit 7 in the second register 10 on all control cycles, except the first.

The first control cycle is identified by the element OR-NOT 6, a single value at the output of which is formed with a zero code at the information outputs of the first counter 3.

Thus, in the first register 2, the information element is recorded only in the first control cycle of one element, and the element with the number indicated by the second counter 4 is recorded. At the end of the first control cycle, the third counter 5 records a code defining the length of the controlled sequence I, which the front generated by the element HE 14 when moving to the second control cycle is entered in the third register 9. The third comparison block 13 generates a zero value at the equality output

5 15

compared codes only when the code recorded on the third register 9 coincides with the code at the output of the second counter A. The equality of these codes means that the next S control cycles will control the last information element of the controlled sequence (where S is the NUMBER of CONTROL CYCLES

one item of information).

A zero value from the output of the third comparison unit 13 sets the input of the installation of a single value to the second trigger 17 in the single state, allowing the third trigger 19 to work on the synchronous input. After passing S control cycles of the last element of the monitored sequence on the front, which generates at the transfer output of the first counter 3, when the next start control cycle signal arrives, the third trigger 19 goes into one state and the zero output from the reverse output of the third trigger 19 occurs in the second counter of the unit code (the code-unit is attached to the information inputs of the second counter t).

Thus, after the control of the last element of the controlled sequence, when the next signal i arrives, the code on the second counter k is recorded not for the 1 + 1, but for the unit, i.e. the control of the first, and later on, all subsequent 1-1 elements of the controlled information will begin again.

The mismatch of the codes at the outputs of the second counter 4 and the third register 9 leads to the appearance of a single value at the equality output of the third comparison block 13, which permits setting the value of the second trigger 17 along the synchronous input. On the front generated at the output of the element HE 14 at the end of the first cycle of control of the first element of the controlled sequence, the second trigger 1 is set to the zero state, reset to the zero state and the third trigger 19.

Consequently, throughout the entire monitoring time, the code at the output of the second counter, k, will cyclically vary from 1 to 1, forming all the numbers of the monitored elements

J JQ

20 25 30

35

40

five

five

126

com information. Thereby, idle cycles are eliminated.

The first comparison unit 7 performs a one-by-one comparison of the values of the signals coming from the monitored information input 20 and from the output of the first register 2. The bit comparison result is entered into the second register 10 in all control cycles except the first, only when applied to the inputs of the first block 7 comparison of information elements with the same numbers, and from the output of the first register 2, the element recorded in it in the first control cycle is removed. When all the bits in the second register 10 coincide, the zero code is entered, which is identified by the element OR 12. If the values of the information elements at the output of the element 16 do not coincide, a single value is generated that arrives at the synchronous input of the first trigger 18 and sets its zero state, thereby prohibiting the passage of signals oi through the first element I 1. At the same time, the zero value of the signal from the output of the first flip-flop 18, which is the output 2A of the monitored information, stops the flow of pulses synchronization from the controlled object to the clock input 21, and also indicates the presence of an unstable failure in the controlled information.

The outputs of the display unit 15 receive codes from the outputs of the second register 10 and the second counter k, thereby inducing the element bits and the number of the information element itself, for which an unstable failure is detected.

Claims (1)

Invention Formula A device for 1 fixation of unstable failures, containing the first and second elements AND, the first and second registers, the first, second and third counters, the OR-NOT element, the first and second comparison blocks, the display unit, the OR element and the first trigger, and the trigger input the control loop of the device is connected to the first input of the first element I, the second input of which is connected to the output of the first trigger, and the output of the first element I is connected to the counting input of the first counter, the information outputs and the overflow output of which are connected respectively to by the inputs of the OR-NOT element and the counting input of the second counter, the information output of the second counter is connected to the first information input of the first comparison unit and the first input of the display unit, the information output of the third counter is connected to the second information input of the first comparison unit, the equality output of which is connected to the first input of the second element AND, the second input and output of the second element AND are connected respectively with the output of the element OR NOT and the synchronous input of the first register, the output of which is connected to the first input of the second The second comparison unit, the second input of the second comparison unit and the information input of the first register are connected to the information input of the device, the output of the second comparison unit is connected to the information input of the second register, the output of which is connected to the second input of the display unit, the output of the OR element is connected to the sync input of the first trigger, the output of which is the output of the device, the clock input of the device is connected to the counting input of the third counter, the input of the initial installation of the device is connected to the reset inputs of the second reg Stra, second and third counters, the input for setting the first counter and the input of the installation in a unit consisting of a third flip-flop, characterized in that, in order to increase the reliability of unstable fixation s failures element introduced into the device the ment is NOT, the third element is AND, the third register, the third unit of comparison, the second and third triggers, and the input of the element is NOT connected to the output of the element OR NOT, and the output of the element is NOT with the synchronous input of the third register, with the synchronous input of the third trigger and the second input of the third element And, the first input and output of the third element AND are connected respectively to the output of the equality of the first comparison unit and the synchronous input of the second register, the information input and the output of the third register are connected respectively to the output of the third counter and the first information The second input of the third comparison unit, the second information input and the resolution input of which are connected respectively to the output of the second counter and the start of the control loop of the device, the equality output of the third comparison block is connected to the installation input of the third trigger in one state, the direct output of which is connected to the information input and the setup input to the zero state of the second trigger, the sync input and the inverse input of the second trigger are connected respectively to the overflow output of the first counter and the input set The second counter, the inputs of the OR element are connected to the output of the second register, the comparison resolution input of the first comparison block is connected to the clock input of the device, the installation input of the third register and the input to the zero state of the first trigger are connected to the input of the initial installation of the device a a- " | five: )