SU1145335A1 - Pulse distributor - Google Patents

Abstract

PULSE DISTRIBUTOR, containing a cycle counter, a counter, a clock pulse generator, two blocks of AND elements, characterized in that, in order to expand its functionality, two blocks of registers are entered, a comparison block, a trigger block, a block of counters, a trigger trigger, a trigger, three AND element, OR element, delay element, one-shot, the start code buses are connected to the information inputs of the first register block, whose outputs are connected to the first inputs of the comparison block, the duration codes buses are connected via the second block of registers with information inputs of the counter block, the cycle number bus is connected to the information input of the cycle counter, the zero outputs of which are connected to the inputs of the first element I, the output of which is connected to the R inputs of the start trigger and the trigger, vy1g g ---; -r- I "J 1 I || : l the stroke of which is connected via a delay element to the first input of the second element I, the output of which is connected to the summing input of the counter, the output of the clock generator is connected to the 5 input of the trigger, the second input of the second element I, the control inputs of the comparison unit and the first inputs of the first block elements And, the output of the counter is connected to the second inputs of the comparator unit, the outputs of which are connected to the corresponding 5 secondary inputs of the block of triggers, zero outputs of which are connected to the inputs of the third element And, the output of which connected to the one-shot input, the output of which is connected to the next subtractive input of the cycle counter, R-input of the counter and the first input of the OR element, the start bus is connected to the 5-input of the start trigger and the second input of the OR element, the output of which is connected to the clock inputs of the counter block, the zero outputs of which are connected to the inputs of the second block of elements I, the outputs of which are connected to the corresponding K inputs of the block of flip-flops, the outputs of which are connected to the second inputs of the first block of elements Ni the distributor moves, the outputs of the first block of elements And are connected to the subtractive inputs of the block of meters, and the trigger trigger output is connected to the input of the clock pulse generator.

Description

The invention relates to computer technology and automation and can be used in a pool of control modules with firmware. The known distributor of impulses containing a certain way connected triggers and elements AND Cl3. The disadvantage of this impulse distributor is its limited functionality. Closest to the proposed by the technical nature of the pulse distributor, containing a cycle counter, counter, clock generator, two blocks of elements AND C2 The disadvantage of such a pulse distributor is limited functionality due to the inability to issue pulses with overlapping, of different duration, as well as the inability to change programs output pulse sequence. The purpose of the invention is to expand the functionality. The goal is achieved by the fact that a pulse distributor containing a cycle counter, counter j clock generator two blocks of AND elements, two blocks of registers, a comparison block, a trigger block, a block of counters, a start trigger, a trigger, three AND elements, a delay element ,; one-shot, with bus codes:. Start are connected to the information inputs of the first block of registers, the outputs of which are connected to the first inputs of the comparison block, buses of duration codes are connected via the second block of registers to the information inputs of the block of counters, the bus of the number of cycles is connected to the information input of the cycle counter, zero outputs of which are connected to the inputs of the first element And, the output of which is connected to the R-inputs of the trigger trigger and the trigger, the output of which is connected through the delay element to the first input of the second element And, the output of which Connected to the summing input of the counter, the output of the clock generator is connected to the S-in trigger house, the second input of the second element AND, the control inputs of the comparison block and the first inputs of the first block of elements AND, the output of the counter is connected to the second inputs of the reference current b, the outputs which is connected to the corresponding 5-inputs of the block of triggers, zero outputs of which are connected to the inputs of the third element I, the output of which is connected to the input of the one-vibrator, the output of which is connected to the subtractive input of the cycle counter, the R-input counter a and the first input of the YPI element, the start bus is connected to the 5th input of the start trigger and to the second input of the ShShch element, the output of which is connected to the clock inputs of the counter block, zero outputs of which are connected to the inputs of the second block of elements And, the outputs of which are connected to the corresponding R - the inputs of the trigger block, the outputs of which are connected to the second inputs of the first block of elements AND are the outputs of the distributor, the codes of the first block of elements AND are connected to the subtractive inputs of the block of meters, and the output of the trigger trigger connected to the input of the clock generator. The drawing shows a functional diagram of a pulse distributor. The pulse distributor contains the first block 1 of registers, the second block 2 of registers, block 3 of counters, counter 4 cycles, counter 5, block 6 of comparison elements, trigger7 block 7, trigger 8, trigger 9, clock generator 10 pulses ,. the first block 11 And elements, the second block 12 And elements, the first element 13 And, the second element 14 And, the third element 15 And, one-shot 16, element 17 OR, delay element 18, bus 19 start codes, bus 20 duration codes, bus 21 cycle cycles, start bus 22 and outputs 23 of pulse distributor, 1 Tires 19 start codes are connected to information inputs of the first block 1 of registers, whose outputs are connected to the first inputs of comparison block 6, tires 20 of length codes are connected through the second block 2 of registers to information inputs of the block 3 counters, bus 21 number Twa cycles connected to the information input of the counter 4 cycles, zero outputs of which are connected to the inputs of the first element 13 And the output of which is connected to the R-input of the trigger 8 start 3 ka itrigger 9, the output of which is connected through the element 18 delay to the first input. second element 14 whose output connected to the summing input of the counter 5, the output of the generator 10 clock pulses connected to the 5th input of the trigger 9, the second input of the second element 14 And, the control inputs of the comparison unit 6 and the first inputs of the first block 11 elements And the output of the counter 5 is connected to the second inputs of the block 6 with the corresponding inputs of the trigger block 7, the zero outputs of which are connected to the inputs of the third element 15 And whose output is connected to the input of the one-shot 16, the output of which is connected to the subtracting input of the counter 4 cycles, R is the input of the counter 5 and the first input of the IL element 17; the start bus 22 is connected to the S input of the start trigger 8 and to the second input of the OR element 17, the output of which is connected to the synchronization inputs of the counter block 3, zero outputs of which are connected to the inputs of the second of the element 12. And you Which are connected to the corresponding R inputs of the trigger unit 7, whose outputs are connected to the second inputs of the first block 11 of the elements AND, and are the outputs 23 of the distributor, the outputs of the first block 11 of the elements And are connected to the subtracting inputs of the block 3 of the counters, and the output of the trigger 8 start is connected to the input of the generator 10. clock pulses. The pulse distributor operates as follows. In the initial state, the memory elements of the pulse distributor are in the zero state. Before you start the distributor is setting up. For this, busses 19 start codes in the first block 1 of registers list the start codes of pulses. The tires 20 of the duration codes in the second block of 2 registers register the pulse duration codes, and on the bus 21 of the number of impulses, the code of the number of operation cycles of the pulse distributor is entered into the counter 4. At this point, the setting of the pulse distributor ends with .. The triggering of the pulse distributor is performed by a signal coming 35 through the start bus 22 to the S input of the trigger 8. At the same time, the same signal goes to the element 17 OR, the signal from the output of which is fed to the clock inputs of the block 3 of the counters. The control pulse duration codes are rewritten from the second block 2 of registers to the block 3 of counters. The signal from a single output ° and trigger 8 start is fed to the input of the generator 10 clock pulses and starts it. The first pulse from the generator output 10 clock pulses goes to the S input of the trigger 9. The same pulse goes to the clock inputs of the comparison unit 6. From the single output of the trigger 9, the signal through the delay element 18 is fed to the input of the third element 15 I. This eliminates the first pulse of the generator 10 clock pulses, if there is a zero code for the start of pulses in the first block of 1 registers. The second pulse from the generator output 10 clock pulses enters the input of the third element 15 I, and from its output a pulse enters the input of the counter 5. At the output of the counter 5, a code is generated which is compared in block 6 with the code stored in the first register block 1. When the codes coincide, the output of the comparison unit 6 generates a signal that is fed to the corresponding S inputs of the trigger unit 7. The signal from the corresponding output of block 7 of the trigger is fed to one of the inputs 23 of the pulse distributor. If at the initial moment of time it is necessary to produce pulses simultaneously in several channels, then several triggers of the block 7 of triggers are triggered. The same signal from the unit outputs of the 7 trigger block enters the inputs of the first block of 11 I elements. The signal from the output of the first block of 11 I elements enters the subtraction of the inputs of the 3 counter block in which the pulse duration codes are recorded. From the outputs of block 3 of the counter, signals are fed to the inputs of the second block of 12 I elements. At the outputs of which a signal of the end of pulses is generated, which is fed to the ft inputs of the trigger unit 7. In this case, the triggers of the block 7 of the triggers are transferred to the zero state, and the impulses in the corresponding channels are terminated. Sig511

The bays from the zero outputs of the block 7 of the flip-flops come to the inputs of the third element 15 And, from the output of which the signal goes to the input of the one-shot 16. At the same time, the signal from the output of the one-shot 16 is fed to the input of the element 17 OR and AND-the input of the counter 5. The counter 5 is zeroed. The work cycle is ending. Simultaneously with the resetting of the counter 5, the block 3 of the counter records information about the control pulse duration codes stored in the second block 2 of registers. The cycle of operation is then repeated until reset. 4 cycles counter storing the code of the number of cycles of the pulse distributor.

56

At the end of the pulse output program, the 4-cycle counter assumes the zero state. At the output of the first element 13. And a signal appears, which flips start trigger 8 and trigger 9 to the zero state. At this point, the operation of the pulse distributor ends.

The technical effect of using the proposed pulse distributor is to expand its functional: capabilities by providing the ability to generate pulses of the required duration with the required amount of overlap at the output of the device,

In addition, the pulse distributor is able to output the program recorded in it the necessary number of times.

Claims (1)

PULSE DISTRIBUTOR, comprising a cycle counter, counter, clock, two blocks of AND elements, characterized in that, in order to expand the functionality, two register blocks, a comparison block, a trigger block, a counter block, a start trigger, a trigger, three AND element, OR element, delay element, one-shot, moreover, the start code buses are connected to the information inputs of the first block of registers, the outputs of which are connected to the first inputs of the comparison unit, the duration code buses are connected through the second block of registers with information inputs of the counter block, the bus of the number of cycles connected to the information input of the cycle counter, the zero outputs of which are connected to the inputs of the first element And, the output of which is connected to the R-inputs of the start trigger and the trigger, the output of which is connected through the delay element to the first input of the second element And, the output of which is connected to the summing input of the counter, the output of the clock generator is connected to the 5th input of the trigger, the second input of the second element And, the control inputs of the comparison unit and by the input inputs of the first block of AND elements, the output of the counter is connected to the second inputs of the comparison unit, the outputs of which are connected to the corresponding 5 inputs of the trigger block, the zero outputs of which are connected to the inputs of the third AND element, the output of which is connected to the input of the one-shot, the output of which is connected to the subtracting loop counter input, F-counter input and the first input of the OR element, the start bus is connected to the 5-input of the start trigger and to the second input of the OR element, the output of which is connected to the synchronizing inputs of the counter block whose zero outputs are connected to the inputs of the second block of AND elements, the outputs of which are connected to the corresponding R-inputs of the block of triggers, the outputs of which are connected to the second inputs of the first block of AND elements and are the outputs of the distributor, the outputs of the first block of elements AND are connected to the subtracting inputs of the counter block, moreover, the trigger output of the trigger is connected to the input of the clock generator. 999911 Γ’Τί ^ ί