SU1487067A1 - Unit for searching for data in electronic dictionary - Google Patents

Description

The invention relates to computing, in particular to devices for translating from one language to another, and can be used to automate the process of learning a foreign language. The purpose of the invention is to increase the speed of the device is achieved by applying the method of alphanumeric address tables. In the device containing the input register 2, the code equality circuit 3, the control unit 6 and the memory unit 24, the circuit 4 is additionally entered, the counter 10, the generator 13 clock pulses and the output register 14. 4 Il.

192021

511 „1487067 A1

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1487067

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The invention relates to computing, in particular to devices for translating from one language to another, and can be used to automate the process of learning a foreign language.

The purpose of the invention is to increase the speed of the device.

FIG. 1 is a block diagram of a device for searching information in an electronic dictionary; figure 2 - diagram of the control unit; Fig. 3 is a graph-algorithm of operation of the control unit; 4 shows an example of a fragment of the memory block filling.

The device for searching information in the electronic dictionary has information input 1, input register 2, code equality circuit 3, circuit 4, crash, first input 5 of control unit 6, second input 7 of unit 6, device synchronous input 8, input 9 of the initial installation of the device, counter 10 third 11 and fourth 12 inputs of block 6, 13 clock pulse generator, output register 14, output M ~ bit bus 15 _g , information output device 16, fifth 17 and sixth 18 inputs of control unit 6, first 19, second 20 and third 21 the outputs of the control unit 6, which are respectively clocking, signal outputs and output resolution of the device input, the fourth 22 and fifth 23 outputs of the control unit 6 and the memory unit 24.

Unit 6 control is implemented as a digital machine. One of the embodiments of such a digital automaton is shown in FIG. 2, it contains inverters 25-31 connected according to FIG. 2, elements AND-NO 32-37, elements OR-NOT 38-46 and triggers 47 and 48,

The control unit 6 operates in accordance with the graph shown in FIG.

The operation of the device is based on the use of the method of alphanumeric address tables (BAT) to search for a translation in block 24.

The essence of this method is as follows. Block 24 contains a number of BAT. Each line of such BAT occupies one cell of block 24, the first of the BAT table of the first letters. The digits with numbers from K + 1 to M cells of such a BAT contain the code of one of the letters from which the words included in the logical stock of the device begin. For each letter (namely, in bits 1-K of the corresponding line of BAT of the first letters) there is an address at which the first line of the corresponding BAT of the second letters is written in block 2 в. This table contains the codes of the second letters occurring in the words included in the logical stock of the device after the corresponding first letter. The addresses contained in the lines of this BAT of the second letters are the addresses of the beginnings of the BAT of the third letters appearing after the corresponding combination of the first two letters, etc. Some BAT, except the codes of letters contain a symbol of the end of the word (denoted 0), the address contained in one line BAT with this symbol, is a portion of the translation of code words, the _comparison:. Whose letters with the contents of the relevant BAT possible to obtain the address of the BAT 0 The following portions of the translation of this word are located in subsequent cells. The block of the block 24 with the last portion of the translation code of this word is marked with a unit in the marker M th digit. Similarly marked the last lines of all BAT. The remaining cells of block 24 in the M-th discharge. Contain a zero.

The device works as follows.

At the installation input 9 of the device, an impulse appears corresponding to the “Start” signal, which goes to the zeroing input of the counter 10, resetting it to “0”. At the same time, the zero address goes to the input of the unit 24 from the output of the counter 10. After that, the output of block 24 appears the contents of the first cell BAT first letters, This information on the decline of the clock pulse coming from the generator 13 clock pulses to the control input of the register 14, is recorded in this register.

The "start" signal is also supplied to the third input 11 of the control unit 6. The latter, according to the graph-algorithm (Fig.'Z), enters the state 00 and generates a signal at the output 21 of the input device permission

In such a state, the device is located before entering the information input 1 of the device code first

letters of the word being translated and on sync1487067

the input 8 of the sync pulse, according to which the code of the first letter is written to the input register 2, the signal of the synchronous input 8 is fed to the second input 7 of the control unit 6 and the decay of the pulse coming from the clock generator 13 to the fourth input 12 of the control unit 6, translates it 01 according to the algorithm graph (fig. 3). The control unit removes the signal from the output 21 input permission. The code of the first letter from the output of the input register 2 is fed to the first input of the circuit 3 of equality of codes, the second input of which receives the code of the first letter of the BAT of the first letters.

If the entered letter does not coincide with the letter recorded in register 2, on the leading edge of the clock pulse coming from the generator of 13 clock pulses to the fourth input 12 of the control unit 6, this block outputs to the fourth output 22 a signal which, acting on the counting input of the counter 10 , adds a unit to its content. From the output of the counter 10 a new address is fed to the input of block 24. The output of the second cell of the BAP of the first letters appears at its output. The decline of the clock pulse coming from the generator 13 clock pulses to the control / input of the register 14, the contents of the next cell is written to this register and the code of the second letter of the first BAT is fed to the second input of the circuit 3 equality of the codes, Also, the clock drop from the generator 13 clock pulses, the control unit 6 removes the signal from the fourth output 22 and the transition in accordance with the algorithm in FIG. 3 to the same state 01. The operation of the device continues similarly until the equalization circuit 3 issues on the input 16 of the control unit 6 signals the coincidence of the codes of the letter entered in the input register 2 and the letter in bits from K + 1 to M-1 register 14,

In this case, on the leading edge of the clock pulse, the control unit 6 according to the graph algorithm in FIG. 3 outputs a signal to the fifth output, which is fed to the control input of the counter 10, and the address of the first cell of the corresponding BAT of the second letters is recorded in the counter.

This address enters the input of block 24, reads the contents of the first cell of the corresponding BAT of the second letters, which is written to the register 14 by the decay of the clock pulse. After the decay of the same pulse, the control unit 6 goes to state 00, removes the signal from the fifth output 23 and outputs a signal to the third output 21 of the input permission of the device.

The operation of the circuit continues similarly until the end-of-word code arrives at the information input 1 of the device. Then, the signal at the synchronous input 8 of the device is recorded in the input register 2, and then fed to the input 4 of the coincidence circuit, which outputs the signal to the first input 5 of the control unit 6.

Next, operation of the apparatus takes place according to the algorithm described before receipt of a signal from the circuit 3 equalities codes at the sixth input 18 of the control unit 6, wherein at the rising edge of the clock pulse at the fifth output signal is 23, the control unit 6. Arriving at run ^one conductive input of the counter 10 , at the same time the address of the cell with the code of the first portion of the transfer is recorded in the latter. The address is fed to the input of block 24, from which the first portion of the translation is read, which is written to the register 14 by the falling edge of the clock pulse and is fed to the information output 16 of the device. The control unit 6 on the falling edge of the same pulse passes to state 11 (FIG. 3). Upon receipt of the following. clock pulses on the control unit 6 on its first output 19, a synchronizing output information signal appears. At the same time, a signal appears at the fourth output 22 of the control unit 6, adding 10 to the contents of the counter. The new address is fed to the input of block 24, and the next portion appears at its output, which is recorded at the falling edge of the clock pulse in the register 14 and fed to the information output 16 of the device. On the falling edge of this pulse, control unit 6 removes signals from the first 19 and fourth 22 outputs.

The scheme works similarly until register 14 is written

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the contents of the cell with the code of the last portion of the translation. In this case, the unit of the M th marker discharge of the bus 15 is fed to the fifth input 17 of the control unit 6 and, on the leading edge of the clock pulse, it outputs a signal to the first output 19. After the pulse drops, the control unit 6 goes to state 10, removes the signal from the first output 19 and issues a signal to the second output 20, signaling the end of the device operation,

If the entered letter is not recorded in the BAT, t, e, the equality circuit 3 all the time gives 0 to the sixth input 18 of the control unit 6, when viewing the last cell of the current BAT to the fifth input 17 of the control 6 comes from register 14 a single signal one marker discharge. Then, on the decline of the clock pulse, the control unit 6 switches to the state 10 and outputs a signal to the signal output 20 of the device, signaling the completion 25 of the operation of the device. In addition, if necessary, the device at any time can be returned to its initial state by the “Start” signal, supplied to the control input 9 of the device, one

Claims (1)

Claim A device for searching information in an electronic dictionary containing an input register, a control unit, a comparison circuit, a memory unit, an input register output connected to the first input of the code equality circuit, from; citing the fact that, with ce-; With increased speed, it σόη holds a coincidence circuit, a clock generator, a counter and an output register, the information inputs of which are connected to the information ones. the outputs of the memory block, the input register output register is connected to the output of the clock pulse generator, the output register input is connected to the information input of the coincidence circuit, the output of which is connected to the first input of the control apple, the second input of which is the device synchronization input and the third the input of the control unit is the input of the initial installation of the device and is connected to the reset input of the counter; the fourth input of the control unit is connected to the output of the clock pulse generator c, the fifth input of the control Bppoc is connected to the output of the Mth digit of the output register (where M is the width of the output register), the sixth input of the control unit is connected to the output of the code difference circuit, the second input of which is connected to (K + 1) th (M-1) -th information outputs of the output register (where K is the width of the address code of the memory block, which determines its capacity, K is always less than M), the first to K-th information outputs of the output register are connected to the information inputs of the counter, information outputs which are connected to address inputs the memory block, the first, second and third outputs of the control unit are clocking respectively, and the signal outputs and the output resolution of the device input, the fourth and fifth outputs of the control unit are connected respectively to the counting input and output of the parallel counter load, the information input of the input register is the information input of the device, the information output of the output register is the information output of the device. 1487067 0 <ίί. 2 I * & 1Г * п / Уц I" *"*"/*" *"/*and 9Sh.Z X »xMz * n 1487067 Aires Information In the bits of the storage device I have a word related information Rod information. 1 to K + 1 ... <- / one 0 362 BUT 0 BUT.·.  - 37 ^ - <3 d at... 9 • at 9 the first 9 • © 9 " * 9 © letters 490 Ζ / Ζ ... © at 9 " 9 9 © © at © © 9 • • © " • • "Th < at at AO · .. 6Ή ............. n <? AN ··. £ A7 9 © " © © 9 Second © © .. ® __ ... e . ♦. . . Zuhd x --------- 4Ζ ... © 9 © © • 9 " © ·. 9 • 9 © © © • •. 9 five// 7th BUT f L * / about g 115 *. ..... f AN * © © • © © f • © © 9 © F © © © third <? ear © & © © 9 © 9 © ' at 9 f © © f 9 "7? G Gpvziiiya f 715 L position f m new 411 ΪΖ position f translation YAH / SZTLA © 9 © at 9 & 9 © 9 9 © © © © •. Thebes. four