SU1665373A1 - Associative summing device - Google Patents

Abstract

The invention relates to computing and can be used in devices for processing arrays of numbers. The aim of the invention is to increase speed. To do this, a fourth group of And elements and a sum encoder are introduced into the device containing a permanent storage block, an associative storage block, three groups of AND elements, an And element and two groups of delay elements. The device implements a sequential-by-bit and word-by-word summation method. The increase in speed is achieved due to the fact that the device does not make additional cycles of summation of carries, but ignores the higher bits of the sum in the parallel code from the carries. 2 Il.

Description

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The invention relates to computing and can be used in devices for processing arrays of numbers.

The aim of the invention is to improve the speed of the device.

Figure 1 shows the structural diagram of an associative summing device; Fig. 2 shows the layout of information in the units of the device for summing five terms.

The device contains a persistent storage unit 1, an associative storage unit 2, a group of 3 elements AND, an element 4, a group of 5 and 6 elements I. a group of 7 and 8 delay elements, a group 9 of elements I and an encoder 10 amounts that can be executed for example, on the basis of an associative memory block (figure 2). The device has 11 inputs, the first output is 12 sums, the second

output 13 sums and bus 14-16 sync.

The device works as follows.

The device inputs 11 simultaneously feed the same-named bits of the K items with a digit 1, which determine the address of the word read from block 1 during a clock pulse. The word read from block 1 is itself a part of the characteristic applied to the polling inputs of block 2, moreover, all bits, except the younger one, are delayed by one clock cycle. The rest of the tag is all but the most significant bit read from block 2 and delayed by one measure.

The formed feature is additionally synchronized on the AND 4-6 elements by sending a signal over the bus 15, the leading edge of which starts later, and

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the back one is before the clock pulse sent over the bus 14. This measure is caused by the imperfection of the delay elements 7 and 8.

In the same cycle in which the bit slice of the terms was applied, the output of 12 of block 2 is followed by the next bit of the sum. Thus, the first output is the first part of the result of the summation in the sequential code, and the number of cycles for which the first part of the sum result is equal to the sum of the terms.

The second part of the result of the sum is formed at the outputs 13 of the block 10 by sending a signal along the sync of the device 16. The encoder 10 encrypts the higher bits,

Claims (1)

Invention Formula An associative summing device containing a permanent storage unit, an associative storage unit, three groups of elements AND, an element And, two groups of delay elements, the first input of an element AND is connected to an output of a lower bit of a permanent storage unit whose address inputs are connected to the outputs of the corresponding elements And the first group, the first inputs of which are connected to the device’s first synchronization bus, and the second inputs are connected to the corresponding inputs of the device’s components, the second input of the And element and the first the inputs of the elements of the second and third groups are connected to the device’s second synchronization bus, the outputs of the elements of the second and the third group is connected to the corresponding bits of the polling input of the associative storage unit, the output of the lower bit of which is the first output of the sum of the device, the outputs The bits of the constant memory block, except the low bit, are connected via the corresponding delay elements of the first group with the second inputs of the elements AND the second group, the bits of the associative memory block, except the low bit, are connected via the corresponding delay elements of the second group to the second inputs of the elements And the third group, characterized by that, in order to improve speed, the device additionally contains a fourth group of elements And a sum encoder, the inputs of the delay elements of the first and second groups are connected to the first inputs of the corresponding elements AND of the fourth group, the second inputs of which are connected to the third synchronization bus of the device, and the outputs are connected to corresponding encoder input bits the amounts whose outputs are connected to the bits of the second output of the sum of the device. Phie.1 I VVV 13 Fig 2 YU