SU1413640A1 - Device for simulating activity of human operator - Google Patents

Abstract

The invention relates to computing, in particular, to devices for simulating the activity of a human operator of a human-subject system. The purpose of the invention is to expand the functionality of the device by simulating the performance of an emergency algorithm when a failure occurs. The purpose of the invention is to introduce into the device two groups of AND elements, OR elements, OR group of elements, a trigger, a memory block, a number of correctly executed operations and a key . The device can simulate the occurrence of an emergency with any operation of the main control algorithm and determine which situations require repair personnel, and in which cases the operator is able to independently perform the control task in the allotted time interval (standard). 1 il.

Description

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The invention relates to computing 5, in particular, to devices for simulating the human operator of a man-system mapin system.

The purpose of the invention is the expansion of the functional capabilities of the device by simulating the performance of work on the emergency algorithm for BOS failure.

The drawing shows a diagram of the device. The device contains the third element HJDi 1, the second trigger 2, the first element OR 3, the second element AND 4, the second element 5 delay, the third element 6 delay, the third element And 7, the first memory block 8, the first group 9 elements And, the fourth element And 10, the second memory block 11, the ninth element AND 12s the first delay element 13, the group of elements OR 14, the memory register 15, the first trigger 16, the generator 17 pulses of a random ... .- duration J; D4x}) transcending element ment 18, generator 19 of uniformly distributed numbers, converter 20 time1 interval, the code and the first comparison circuit 21, first element AND 22 ,, sixth element AND 23, failure counter 24, fifth element AND 25, eighth 26 and seventh 2.7 element AND, registration unit 28, second comparison circuit 29, adder 30, fifth element OR 31 , the first counter-to 32, the number of correctly executed operations, the fourth element OR 33, the second counter 34, the number of correctly executed operations, the third comparison circuit 35, the second element 36, the counter 37 of completed implementations, the second group of elements 38, the key 39 dec the second element 40 and the mode device start input 41.

Unit 8 is intended for storage and entry into the register 15 of the parameters of the control algorithm. It stores information about the control and operational components of the activity algorithm, the execution of which is modeled by the operator.

The memory unit 21 is intended for storing and delivering to the register 15 the parameters of the emergency (troubleshooting, failure) algorithm. It stores information about the control and operating components of the emergency activity algorithm, which the operator must perform, interrupting the main

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algorithm. Data is read from memory blocks 8 and 11 by sending signals to their inputs, while at the time of the signal at the first input of the memory block, the parameters of the first and all subsequent operations of the algorithm are generated, and when the signal at the second input appears Each block of memory provides data only on the first operation of the corresponding algorithm (main and control), which corresponds to the beginning of a new implementation of the simulation for a set of statistically reliable number of res. In this case, the appearance of the signal at the first inputs of the memory blocks corresponds to either the first or the next implementation, provided that the previous implementation was completed successfully, and the appearance of the signal at the second input of each memory block corresponds to the situation when the previous implementation was unsuccessful, those. control algorithm was not executed. Both blocks of memory are divided into two zones, and in their first zones the values of the mathematical expectation and the standard deviation of the execution time of each type of elementary operations included in the main and emergency algorithms, respectively, are stored. These values are placed in the order of the following operations when performing the specified algorithms. In the second zones, the probability values of the error-free execution of the corresponding type of elementary operations of the algorithms P / are located, which make it possible to assess the error-free operation of the operator taking into account the layout of the display panels and control of the relevant authorities. These parameters characterize the operational component, and the order of the operations follow the control component of the simulated algorithm.

Register 15 stores and issues on the first output the values of mathematical expectation and standard deviation, and on the second output, the values of P operations of the corresponding (their algorithms.

The delay elements 5, 6 and 13 are designed to synchronize and organize reliable writing and reading data from memory blocks 8 and 11 into register 15. In addition, delay element 5 is selected taking into account the time

trigger 2 and the time of operation of the first counter of the number of correctly performed operations during the execution of the emergency algorithm.

The generator 17 forms a sequence of pulses of random duration distributed according to the necessary law with parameters outputted from the first zone to the first outputs of memory blocks 8 and 11.

The generator 19 uniformly distributed in the interval (0-1) random numbers generates random numbers corresponding to the likelihood of the operator performing the elementary operation of the algorithm. Power is supplied to generators 17 and 19 by a signal that triggers the operation of the device, power supply circuits are not shown according to the device diagram.

The differentiating element 18 separates the start pulse and the pulse end pulse of a random length generated by the generator 17 to further convert the length of time (pulse duration) into the code in the time converter 20 and the interval-code.

The adder 30 performs the summation of all values of the time intervals for performing operations both for one and for all operations of the control algorithm and for all its previous implementations. If an error is committed when executing the operator control algorithm, i.e. the control algorithm is not executed, the values of all the time estimates for this operation in this implementation are erased and with erroneous implementations are not summed,

In comparison circuit 21, upon receipt of a pulse. End from element 18, a random comparison is made.

the numbers Xp, previously generated by a command from the output of the third delay element 13 by the generator 19, with the probability value of the error-free execution of the current operation of the algorithm rewritten into the register output comparison circuit 27 15. As a result of comparing these numbers, the current operation of the algorithm is determined to be error-free. If, then the operation is considered completed correctly. Otherwise, an error is fixed and the simulation of this i implementation ends there. Serving

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the signal to the second read input of any of the memory blocks is provided by simulating the next implementation from the first operation of one of the algorithms.

The counter 32 counts the number of correctly executed operations in the main control algorithm for further comparison in comparison circuit 35 with the number of operations contained in the control algorithm, which makes it possible to determine when the operator completes the tasks and control and proceed to the next implementation of the algorithm. In addition, the counter 32, after it counts a certain number of algorithm operations performed (this number is set in advance before the simulation), issues a signal at the second stage of the study to process the alarm algorithm, while the counter is turned off and starts to work only after the successful completion of the alarm algorithm when the operator goes to perform the remaining operations of the main algorithm. This moment is repeated at the second stage in each new implementation and can be played for any operation of the main algorithm and the corresponding emergency algorithm, taking into account the situation that has arisen,

The counter FOR counts the number of correctly executed operations in the emergency algorithm. As soon as the operator makes a mistake, in the emergency algorithm, the counter is reset and the implementation of the emergency algorithm is repeated. The number of operations of the alarm algorithm is preset on the counter. As soon as the counter counts the necessary number of correctly executed operations, it gives the command to continue the execution of the axial control algorithm.

The number of operations of the main algorithm; The control mode is set up in comparison circuit 35 before starting the simulation.

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Counter 37 counts the number of implementations of the algorithm performed, both successful and erroneous for the circuit 29 comparing with the required number of implementations. This number is recorded in the comparison circuit 29 also before the start of the simulation and is determined by the rate of the required accuracy of the simulation results.

Counter 24 counts the number of errors made during the execution of the control algorithm (without taking into account errors during the execution of the emergency algorithm), which corresponds to the number of unsuccessful implementations, i.e. attempts to execute the algorithm.

Block 28 registers at the end of the simulation the number of unsuccessful attempts to execute the algorithm, i.e. the contents of counter 245 as well as the value of the total simulation time of all successful implementations of the control algorithm, i.e. the contents of the adder 30.

The trigger 16 controls the on and off of the modeling device. Trigger 2 controls the process of delisting the control algorithm before and in the event of an emergency.

The number of items in the first. the group of elements AND 9, the second group of elements AND 38 and the group of elements OR 14 correspond to the size and number of parameters stored in the first 8 and second 11 memory blocks.

The study is carried out in two stages: 1) without taking into account the emergency situation before the set of necessary statistics of the results and 2) research and quantitative assessment of the quality of the operator's activity taking into account the emergency algorithm.

Consider the operation of the device at the first stage of modeling (key 39 is open in this case). After the start signal is applied to the input 41 of the device, generators 17 and 19 are turned on, the first of which is prepared to form a sequence of pulses of random duration, and the second to generate random, uniformly distributed numbers. In addition, the start pulse through the first element OR 3 arrives at the delay element 5, the delay time of which is set depending on the output time for a given operating mode of the generators 17 and 19. The start pulse through the element OR 1 is fed to the single trigger input 2, from the direct output of which the signal goes to a group of elements AND 9, ensuring the passage of information from the 8-unit memory to the memory register 15. The signal from the output of the trigger 2 is supplied to the element And 25 to allow transmission of signals from the comparison circuit 21 to the counter

32 numbers of operations performed successfully in the main algorithm of the operation and to the adder 30 through the fourth element OR 31. In addition, the signal from the direct output of the trigger 2 is fed to the inputs of the And 7 and 10 elements providing cooling of the signals to the memory block 8. The inverse output of trigger 2 excludes participation in the operation of the device of memory block 1G, counter 34 by closing elements 4 and 13, as well as elements 27 and 40. After the signal from the delay element 5 arrives at the first read input of memory 8 through the open element 7 is compiled from the zones to the register 15 to simulate the execution of the first operation of the control algorithm. In addition, the signal from the delay element 5 is fed to the delay element 6, the delay time of which is selected based on the duration of the rewriting of information from memory block 8 to memory register 15. The signal from the delay element 6 is fed to the input of the delay element 13 and to the input of the recording permission register 15. This signal overwrites the values of the parameters of the operating component of the simulated operation into the generator 17 and the comparison circuit 21, respectively. The generator 17 starts forming a sequence of pulses of random duration, which are fed to the input of the differentiating element 18. The delay time of the delay element 13 ensures reliable reading of information from the memory register 15. The Start signal from differentiating element 18 is fed to the start input of converter 20, the time interval is the code, and the End signal to the stop input, which forms the code for the duration of the time interval. At the same time, the End signal gives a comparison command in the first comparison circuit 21, in which a random uniformly distributed number is compared with the probability value of an error-free operation of a given clock cycle. If the operation is considered to be completed without error and the output pulse of the comparison circuit 21 arrives at the first input of the And 22 element, In the presence of a low frequency signal, the second input, if not all operations of the control algorithm B1 1 are complete, this signal is applied to the input of the element OR 3 and the entire cycle of operation of the device (already for modeling the second operation of the control algorithm) is repeated. In addition, the pulse from the output of the comparison circuit 21 is fed to the input of the adder 30. through the OR element 31 and the input of the counter 32 through the And 25 element. The adder 30 consists of two blocks, the first time the operation time of the current implementation of the algorithm is calculated, and the second time previous successfully completed implement. If the implementation is completed successfully, the simulation time is summed with the contents of the second block due to the appearance of a signal at its second setup input; otherwise 5 i.e. if the implementation is unsuccessful, the signal at the first installation input of the adder 30 nulls the contents of the first block. From the output of the counter 32, the number of successful operations goes to the comparison circuit 35, from which a constant single signal is removed until all the operations of the control algorithm have been performed. When all operations of the algorithm are completed successfully, a single pulse from the output of the comparison circuit 35 is sent through the OR 36 element to the counter 37 to count the total number of implementations. At the same time, the signal from the output of the second OR 36 element enters the counter 32 and zeroed em its contents, preparing it to count the number of successful operations in the next implementation, as well as the input of the first element OR 3 to start modeling the next implementation of the control algorithm and the input of the counter 34 through the element OR 33, resetting counter 34 and preparing it to count the number of successful operations in the emergency algorithm (in the case of modeling the operator's work on the execution of the control algorithm taking into account the emergency situation - at the second stage of the study). From the output of the comparison circuit 29, the signal to the trigger 16 does not arrive until the required number of implementations has been calculated. If, when compared in the comparison circuit 21. , the operation is considered unfulfilled, as is the entire control algorithm. In this case, the signal from the output of the comparison circuit 21 is fed to the counter 24 failures through

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oTi CpbiTbul element AND 23 ll counting the number of unsuccessful decisions of the control algorithm, to the input of the element lUIH

36 for counting the total number of implementations of the control algorithm in the counter

37 the number of implementations and zeroing of the counters 32 and 34 through the OR element 36. In addition, the signal from the output of the AND 23 element wraps the contents of the first block of the time adder spent on the current implementation of the control algorithm. The signal from the first output of the first comparison circuit 21 is fed to the second input of the memory block 8 of the memory through the element 10 and provides the output to the register 15 of the data of the first operation of the algorithm for simulating its next implementation. When the number of implementations of the control algorithm reaches the required number, the signal from the output of the comparison circuit 29 is fed to the input of the counter 24 to read information into the register 28, as well as to the read input of the adder 30, according to the signal of which the total simulation time of all successful implementations is also written to block 28 registration.

In the second mode of operation, the modeling device, i.e. taking into account the emergency, the key 39 is closed. The launch of the device and the operation of the device for simulating the performance of operations preceding the one on which the emergency situation is created is similar to the order of operation of the device described earlier. In addition, the counter 32 counts the number of correctly executed operations of the control algorithm; it outputs a signal to the 2 trigger input via the closed key 39, and the signal to the second trigger 2 arrives after the end of the simulation of the next operation. The number of correctly executed operations in which the counter 32 outputs a signal to the second trigger 2 is set before the start of the second simulation mode. With the arrival of the signal from the counter 32, the trigger 2 goes to the zero state, excluding the participation in the simulation process of the first memory block by means of And 7 and 10 elements, counters 32 and 24 through And 25 and 23 elements respectively. In addition, the trigger 2 in the new state ensures participation in the simulation process of the second memory block 11 by means of

elements 4 and 12, as well as the participation of counter 34 for counting the number of correctly performed operations in the emergency algorithm by means of element 27. From this moment, the simulation of the emergency algorithm that is embedded in the main control algorithm begins. The order of reading information occurs from memory block 11 is similar to that described previously, except for the operation of the device after the comparison circuit 21. So, after correct execution of the emergency algorithm operation, the signal from the second output of the first comparison circuit 21 goes to the counter 34, the number of correctly executed operations through the element K 27 and the element OR 31. All correctly executed

: the emergency algorithm operations are counted in the counter 34, and the simulation time for performing the emergency algorithm operations is counted in the adder 30 (both successful and erroneous implementations of the emergency algorithm) and is included in the total simulation time for the implementation of the control algorithm. Since the counter 32 has stopped and the element AND 25 is closed, then. for the time of the simulation of the emergency algorithm from the comparison circuit 35, the signal is continuously fed to the element 22, which ensures the process of modeling all operations of the emergency algorithm. As soon as the counter 34 has the number of correctly executed operations and their number equals the number of operations of the emergency algorithm (this number is set before the second stage simulation), then the signal for trigger 2 is output from the counter through the OR element 1, which stops the simulation of the emergency algorithm and

provides continuation of the interrupted process of modeling the main control algorithm. The counter 32, the memory block 8 are then prepared for operation, and the counter 38 and the memory block 11 are also turned off. The subsequent work continues in the same way as the simulation of the control algorithm in the first stage of the study described earlier. If, during the simulation of the emergency algorithm, the operation is counted incorrectly, then the signal from the first output of the comparison circuit 21 goes to the counter 34 through the OR element 33 and embeds it, preparing it for operation

emergency algorithm in the new implementation. In addition, the signal from the comparison circuit 21 is fed to the adder 30 through the element 26 and the element hjffl 31, providing time counting, and to the read input of the second memory block 11 through the element 12, ensuring the issuance of a new implementation

the emergency algorithm, as well as the signal from the first input of the comparison circuit 21 through the open element AND 40, is fed to the input of the element OR 3 to begin modeling the new implementation of the emergency algorithm and so on until the emergency algorithm is completed successfully. After the proper execution of the emergency algorithm, the simulation of the main control algorithm continues.

The obtained data allow us to estimate the characteristics of the quality of operator activity with known methods, taking into account possible accidents.

situations. In this case, it is possible to simulate the occurrence of an emergency with any operation of the main control algorithm and determine for; which situations require the call of repair personnel, and in which cases the operator is able to independently perform the control task in the allotted time interval (standard).

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Claims (1)

Invention Formula A device for simulating human operator operations, containing the first and second elements OR5 the first element AND, the first, second and third elements of the delay, the first memory block, the memory register, the first trigger, a generator of pulses of random duration, a differentiating element, a generator of uniformly distributed random numbers, time interval converter — code, first, second and third comparison schemes, failure counter, registration block, the adder, the first counter of the number of correctly performed operations of the main control algorithm and the counter of the number of completed implementations, the bit outputs of which are connected to the first input of the second comparison circuit, the output is connected to the first input of the first trigger, the reset input. failures, readout input from M-G, information inputs which is connected respectively to the converter outputs time interval — the code whose start input is connected to the first output of the differentiating element, the second output of which is connected to the converter stop input, time interval — the code and the comparison input of the comparison circuit, information inputs: the first group of which are connected respectively to the outputs of the generator of uniformly distributed random numbers, the start input of which is associated with the output of the first delay element and the reset input of the register pa The first group of bit outputs of which is connected to the information inputs of a pulse generator of random duration, the output of which is connected to the input of the differentiating element, and the second group of bit outputs of the memory register is connected respectively to the information inputs of the second group of the first comparison circuit, the output is Less or Equal to which is connected to the first input of the first element AND, the output of which is connected to the first input of the first element OR the second input of the first element AND connected to the output Less than the third circuit By comparison, the output of which is connected Equal to the first input of second OR input of the adder and the mounting, the overflow output of counters failures connected to the first data input of the recording unit, second information input of which is connected to the output of the adder to the counting input of counter realizations formed connected to the output of the second the OR element and the zeroing input of the counter of the number of correctly performed operations, the first group of bit outputs of which are connected respectively to the information inputs of the third comparison circuit, the zero input of the first flip-flop is a device start input and connected to the second input of the first OR element, the output of which is through the second delay element connected to the input of the third delay element, the output of which is connected to the input of the first delay element and the memory register read input, characterized in that, in order to expand neither the functionality of the simulation due to the performance of work on the emergency algorithm with five 0 five 0 five 0 five 0 five rejects of failures, it additionally contains the first and second groups of elements I, from the second to the tenth elements I, the third, fourth and fifth elements of SH, group of elements SH, second trigger, second memory block, second counter of the number of correctly executed Operation 1-1 and key; the first input of the third element OR is connected to the device start input and the first 1 output of the first trigger is connected to the memory register zeroing input, the group of the bit inputs of which is connected respectively to the outputs of the elements of the OR group, the first inputs of which correspondingly connected to the outputs of elements AND of the first group, the second inputs of the elements OR of the group are connected respectively to the outputs of the elements AND, the first inputs of which are connected respectively to the outputs of the second memory block, the first input of which is connected to the output of the second element And, the first input of which is connected to the output The second delay element and the first input of the third element And whose output is connected to the first read input of the first memory block, the outputs of which are connected respectively to the first inputs of the elements And the first group, the second inputs of which are combined and connected to the second input of the third element And, the forward output of the second trigger, the first input of the fourth element And, the first input of the fifth element And and the first input of the sixth element And, the second input of the fifth element And and the first input the seventh element AND is connected to the output Less or Equal to the first comparison circuit, the output More than which is connected to the first input of the eighth element AND, the first input of the fourth element OR, the second input of the fourth element AND, the second input of the sixth element AND, the first The input of the ninth and tenth elements is And, the output of the sixth element And is connected to the counting input of the failure counter, the zeroing input of the adder and the second input of the second element OR, and the output of the fourth element AND is connected to the second read input of the first memory block, the second read input of the second the memory unit is connected to the output of the ninth element And, the second input of which is connected to the second input of the second element And, inverse