SU1377870A1 - Device for simulating activity of a human-operator - Google Patents

Abstract

The invention relates to computing, in particular, to devices for simulating the activity of a human operator of a system - Man-Machine. The purpose of the invention is to expand the functionality of the device by simulating the operator's activity in the presence of logical conditions in the algorithm of operation. The device contains a microprogram memory block, microinstructions register, first, second and third delay elements, first, second and third OR elements, adder, error counter, first AND element, correctly executed operations counter, first trigger, first, second and third circuits comparison, counter of completed implementations, registration unit, the first generator of uniformly distributed random numbers, a pulse generator with a random duration, a differentiating element, and a time interval-code converter. The obtained data in the registration unit allows one to estimate the main characteristics of the quality of the ACS operator performance when executing complex algorithms using known methods. 1 il. i (L

Description

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The invention relates to computing, in particular, to devices for simulating the activity of a human operator of the Man-Machine system.

The purpose of the invention is the extension of the functionality of the account of modeling the operator's activity in the presence of logical conditions in the algorithm of operation.

The drawing shows a block diagram of the proposed device.

The device for simulating the activity of a human operator contains the register of microcommand address 1, the first element is NOT 2, the first element is OR 3, the microprogram memory block 4, the second element is AND 5, the first delay element 6, the fifth element OR 7, the counter 8 position control is a logical operation, the second element is NOT 9, the third element is AND 10, the register of 11 micro-commands the second element 12 of SHS, the first trigger 13, the driver of 14 pulses, the second delay element 15, the second generator 16 of uniformly distributed random numbers, the fourth delay element .17, third element 18 delays, 19 totals generator with random duration, first 1 1st generator 20 uniformly distributed random numbers, first register 21, fourth comparing circuit 22, differentiating element 23, time interval transformer 24 - code, first comparing circuit 25, error counter 26 , adder 27, counter 28 correctly executed operations, registration block 29, second trigger 30, third trigger 31, third comparison circuit 32, first AND element 33, first AND block 34, second AND block 35, third element OR SH 365 counter 37 executed pea - the localization, the second register 38, the fifth comparison circuit 39, the second comparison circuit 40, the third register 41, the fourth element AND 42, the fourth 43 and 44 the sixth OR elements and the input 45 of the launch of the simulation device.

Register 1 of the micro-command addresses is intended for storing the control component of the algorithm of activity and making the selection of the further required implementation of the modeled algorithm depending on the outcome of the triggering of the logical condition of this algorithm.

The microprogram memory unit 4 is intended for storing and issuing in the register 11 tsarameters of operations of the simulated control algorithm. It stores data on the operational component of the activity algorithm, the execution of which is simulated. These data are read by sending signals to its inputs; in this case, when the signal from And 10 element appears, the parameters of the first and all subsequent operations of the algorithm are increased, and when the signal from block 25 appears, only the first operation of the algorithm is entered into the register. , which corresponds to the beginning of a new implementation of the algorithm, provided that the previous implementation was unsuccessful. In other words, the operator did not perform the control tasks this time. The memory unit 4 is divided into two zones, with the mean of the mean and the standard deviation of the execution time of each type of elementary algorithm operations stored in the first zone. These values are placed in the order of the operations in the execution of the control algorithm. In the second zone, the probability values of the error-free execution of the corresponding type of elementary operations of the algorithm P, are located.

These parameters characterize the operational component, and the order of their following in accordance with the sequence of elementary operations is the controlling component of the simulated activity algorithm.

Elements 6, 15 and 18 of the delay are intended to arrange for reliable writing and reading of data from block 4 of the microprogram memory to register 11 of microcommands.

The counter 8 of the control position of the logical operation in the simulated algorithm scheme is a subtracting counter. In the initial state, it contains the number corresponding to the number of the logical operation of the algorithm (in this case, the number 5). It is designed to start the driver 14 pulses.

Register 11 of microinstructions stores and issues three micro ops arriving from memory block 4.

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The trigger 13 controls the on and off of the device.

The pulse shaper 14 is designed to generate a signal whose duration is equal to the required And 10 blocking duration of the element.

A generator of 19 pulses with a random duration serves to emit pulses of a random duration distributed according to the necessary law with the parameters set by block 4 of the microprogram memory.

The power to the generators 16, 19 and 20 is supplied by a signal that determines the beginning of the operation of the device (power supply circuits are not shown in the device circuit).

In comparison circuit 22, when a pulse delay element 17 is received, the random number Hz, previously generated by a command from the generator of 14 pulses of the generator 16, is compared with a probability value of 25 and the logic condition Rd, which is started by recording, is recorded in register 21 .

Element 23 pulses the impulse and impulse to the ends of the pulses formed by the generator 19 to further convert the belt section to the code in the converter 24.

In scheme 25, the comparison with the arrival of the element 23 of the pulse

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comparison of a random number x, previously performed by a command from the output of the second delay element 15, is made by generator 20 with the probability value for an error-free operation of the given type P, rewritten into the comparison circuit 25 from the register of 11 micro-instructions. As a result of comparing these numbers, the accuracy of the current operation of the algorithm is determined. If . , the operation is considered completed correctly, otherwise an error is counted, the simulation of this implementation is terminated by applying a signal to the second input of the microprogram memory block 4 and the input of the OR 44 element to simulate the next implementation from the first operation of the algorithm.

Counter 26 counts the number of op-boxes made during the execution of the algorithm, which corresponds to the number without 10

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successful implementations, i.e. attempts to implement the algorithm.

The adder 27 performs the summation of all values of the time intervals for executing the operations both for one and for all operations of the algorithm, and for all successful implementations of it. In this case, if, when the algorithm is executed by the operator, an error is allowed, i.e. the algorithm is not executed, the values of all the preceding ones are erased before this operation, and are not summed with error-free realizations.

The counter 28 of the number of correctly executed operations counts the number of correctly executed operations for further comparison with the number of operations contained in the control algorithm, which makes it possible to determine the moment of completion of the operator control task and transitions to the new implementation.

The number of operations of the simulated algorithm, depending on the result of the logical condition, is established in registers 38.41 before the simulation begins.

Block 29 registers at the end of the simulation the number of unsuccessful attempts to execute the algorithm, i.e. the contents of counter 26, as well as the value of the total simulation time

all successful implementations of the algorithm

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those. the contents of the adder 27.

Triggers 30,31 are designed to issue permissive signals for overwriting information from counter 28 into comparison circuits 39.40.

Counter 37 counts the number of implementations performed, both successful and erroneous for comparison in the circuit 32 compared with the required number of implementations. This number is recorded in the comparison circuit 32 also before the start of the simulation and the outcome is determined from the required accuracy of the simulation results.

Elements 1,4 and 11 in aggregate represent a firmware control block, which is a hardware implementation of a mathematical model of an automaton representation of an operator's activity algorithm.

Consider the process of modeling a given algorithm, for example, the following logical algorithm diagram (LSA):

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A1A2AZA4 rHZab; A7A8A9A10A11.

If, when comparing the values in comparison circuit 22, the simulation of the algorithm should proceed after the fourth operation to the seventh operation, i.e. to the choice of the next implementation.

A1A2AZA4A7A8A9A10A11, (1) otherwise, the implementation of the algorithm, namely

A1A2AZA4A5A6A7A8A9A10A1G. (2)

The device operates as follows.

After the start signal is applied to input 45 of the Start device, generators 16, 19 and 20 are turned on, the first and third of which are prepared to generate randomly distributed numbers, and the second to form a sequence of pulses of random duration. In addition, the start pulse through the element OR 3 is fed to the input of the element I5 and to the input of the element 6 of the delay, the delay time of which is set depending on the output to the set operating mode of the generators 16,19 and 20, at the same time

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Circuits: blocks 5-8-14-16-22-1-4 The signal from the output of the 6. Delay element is fed to the input of the E10 element, which is triggered, since at its other input there is a signal from the code of the HE element 9, and the output signal arriving at the first input of the chip of block 4 of the microprogram memory, element E10 reads data from both zones into the register 11 of micro-commands to simulate the execution of the first operation. In addition, the signal from the output of the element And 10 is fed to the input element OR 44, from the output of which it is fed to the element 15 of the delay. The time of its delay is chosen based on the duration of the rewriting of information from microprogram block 4 to the microcommand register 11. The signal from the output of the delay element 15 is fed to the input of the third delay element 18, to the input of the generator 20 of uniformly distributed random numbers and to the input of the read resolution of the register 11 micro-instructions. This signal is used to overwrite the values of the parameters of the simulated operation into generator 19 and comparison circuit 25, respectively. General

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The torus 19 starts forming pulses of random duration that arrive at the input of the differentiating element 23. The delay time value by the delay element 18 ensures reliable reading of information from the register 11. When a signal from the output of the delay element 18 arrives at the installation input of the microcommand register 11, the register is zeroed.

The signal Start from the first output of the differentiating element 23 is fed to the first input of the converter

24 time interval code, and the End signal - from the second output of differentiating element 23 to the second input of the converter 24, forming the code of the duration of the time interval. Simultaneously, the End signal gives a command to compare the first circuit.

25 comparison. It compares the random evenly; distributed number with a probability value of error-free execution of an operation of this type. In the event that., The operation is considered to be completed accurately and the pulse from the second output of the comparison circuit 25 is fed to the input of the And 33. If there is a signal at the second input of the 33 And, i.e. if not all operations of the algorithm are performed, this signal is applied to. the input of the element OR 3 and the whole cycle of operation, but already to simulate the second operation of the algorithm, is repeated. In addition, the impulse from the second output of the comparison circuit 25 is fed to the first information input of the adder 27 and to the information input of the counter 28, the number of correctly executed operations. The adder 27 consists of two blocks, in the first

the simulation time of the current implementation is calculated, and in the second, the time of previous, successfully implemented implementations. If the implementation is completed successfully, then the simulation time will be summed with the contents of the second block of the adder 27 for. the occurrence of the signal at its second setup input, otherwise, i.e. in case of unsuccessful implementation, the signal at the first installation input of the adder 27 will reset the contents of the first block. From the output of the counter 28, the number of successful operations goes to the inputs of the blocks 34,35 of elements AND, which do not work due to the absence of a permissive signal at the control inputs. From the second outputs of the 39.40 comparison circuit, a constant single signal is removed until all operations of the control algorithm (1) or (2) are completed. When all operations of the corresponding algorithm are completed successfully, a single pulse from the first output of comparison circuit 39 or 40 will go through the elements OR 43, 36 to counter 37 to count the total number of realizations. At the same time, the signal from the output of the element OR 36 will go to the installation input of the counter 28 and nullify its contents, thereby preparing it to count the number of successful operations in the next implementation. From the second output of the comparison circuit 32, through the IDI element 12, the second input of the register 11 will receive a signal until the specified

number of implementations. With each successfully rewrite information from the counter 28

In the completed operation, the element And 5 is triggered and the counter 8 each time subtracts the unit from its contents. As soon as the device starts to simulate a logical operation (in this case, the fifth operation) of the algorithm, counter 8 will rob the signal that is fed to the driver 14 pulses, the output pulse that starts the generator 16 of uniformly distributed random numbers. At the same time, the output pulse from the generator 14, whose duration equals the required duration of the blocking element 10, arrives at the input of the delay element 17, at the input of the register 21 and at the input of the element NO 9, which prohibits (until the required implementation of the algorithm is chosen) modeling the next operation . The signal delayed by the delay element 17 at the time of rewriting information from the generator.or 16 and the register 21 to the comparing circuit 22 gives the command to compare the information in the fourth comparing circuit 22. It compares a random uniformly distributed number with the probability value of the logic condition written in the first register 21. In the event that the signal appears at the second output of the comparison circuit 22, at the input of the HE2 element and at the single trigger input 31, with a binary signal

thirty

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and register 38 to comparison circuit 39. If not all operations of the algorithm are performed, the signals from the outputs of circuits 39 and 40 continue to flow to the inputs of AND 42. The output signals of the micro-command address register 1 provide access to the memory areas of microprogram block 4, where the values of the previous operation of the next simulation are stored. e. A6, and when a delayed signal arrives at the first input of block 4, data from both zones will be already combined for operation A7. Further operation of the device in this case has already been described. on.

If, when comparing the values in the first comparison circuit 25, XjiPj is found, then the operation is considered unfulfilled. In this case, from the first output of the first comparison circuit 25, it will go to the counter 26 to count the number of unsuccessful implementations, to the input of the element OR 36 to count the total number of implementations in the counter 37 and zero the counter 28 to prepare it for the new implementation. At the same time, the signal from the first output of the comparison circuit 25 is supplied through the OR element 7 to the installation input of the counter 8, which controls the position of the logical operation in the circuit of the simulated algorithm, and drives it to its initial state. In addition, the signal on the installation

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which permits the rewriting of information from counter 28 and register 41 to comparison circuit 40. If the operations of the algorithm are not all completed, then the signal from the second output continues to flow from both comparison circuit 39 and comparison circuit 40 to AND 42, the output signal of which goes to the input of AND 33. Element AND 33 operates as before The operation was performed correctly and at its input there is a signal from the second output of the comparison circuit 25. The output signal of the element And 33 is fed to the input of the element RIGA 3. Next, the implementation of the algorithm (2) will be simulated according to the described principle.

In that case, when comparing the values in the circuit 22, the signal is received at its first output, at the input of register 1 of the micro-command address and at the single input of the trigger 30, the signal from the output of which allows

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and register 38 to comparison circuit 39. If not all operations of the algorithm are performed, the signals from the outputs of circuits 39 and 40 continue to flow to the inputs of AND 42. The output signals of the micro-command address register 1 provide access to the memory areas of microprogram block 4, where the values of the previous operation of the next simulation are stored. e. A6, and when a delayed signal arrives at the first input of block 4, data from both zones will be already combined for operation A7. Further operation of the device in this case has already been described. on.

If, when comparing the values in the first comparison circuit 25, XjiPj is found, then the operation is considered unfulfilled. In this case, from the first output of the first comparison circuit 25, it will go to the counter 26 to count the number of unsuccessful implementations, to the input of the element OR 36 to count the total number of implementations in the counter 37 and zero the counter 28 to prepare it for the new implementation. At the same time, the signal from the first output of the comparison circuit 25 is supplied through the OR element 7 to the installation input of the counter 8, which controls the position of the logical operation in the circuit of the simulated algorithm, and drives it to its initial state. In addition, the signal on the installation

the input of the sumator 27 will reset the contents of the first block of the adder's time spent on the current implementation. The signal from the first output of the first comparison circuit 25 also goes to the second input of microprogram block 4, providing the first 1.1 data microcommands for the first operation to simulate the next implementation, and the signal from the first output of the comparison circuit 25 to the input of the OR 44 element, is fed to the input element. 15 delays, ensuring that data is written to the register of 11 microinstructions, their reading and starting the generator of 20 evenly distributed numbers.

When the number of implementations of the algorithm reaches a predetermined number, the signal from the output of the circuit 32 s: the equalization will go to the set input of the counter 26 to read information into the registration block 29, to the read input of the adder 27, at a signal from which the total simulation time of all successful implementations will also be written to block 29 registration. At the same time, the signal from the first output of the comparison circuit 32 is fed to the input of the first trigger 13, thus ending the operation of the device

Claims (1)

The obtained data in registration block 29 makes it possible to evaluate the main characteristics of the quality of an ACS operator's performance with the implementation of complex algorithms using known methods. Invention Formula A device for simulating human operator operations containing a microprogram memory block whose outputs are connected respectively to the bits of the micro-instructions register inputs, the first OR element and the first delay element, the second delay element and the third delay element, an adder, and an error counter , the first element And,: the counter of correctly executed operations, the first trigger, the zero input of which is the device start input and is connected to the first input of the first ele cient OR, the first, second and third comparison circuits, a counter formed implementations, block registra- tion, pervsh Generators ator uniformly distributed random numbers, second and third elements Yali, with a random pulse generator The duration 0 five 0 five . .. five 0 five five 0 the differentiating element and the time interval-code converter, the first and second groups of information inputs of the first comparison circuit are connected respectively to the outputs of the first generator of uniformly distributed random numbers and to the information outputs of the first group of the microinstruction register, whose installation input is connected to the BE CODE of the third the delay element, the output of the second delay element is connected to the start input of the first generator of equal-, numbered random numbers and the first input of the resolution of the network The microinstructions register is opened, the second information output of which is connected to the trigger input of a pulse generator with a random duration, the output of which is connected to the input of the differentiating element, the first output of which is connected to the input of the start of the time interval converter code, and the second output of the differentiating element is connected to the resolution enable comparing the first comparison circuit and the converter stop input to the time interval-code, the output of which is connected to the first information input of the adder, the output of which The first information input is connected to the first information input of the registration unit, the second information input of which is connected to the output of the error counter, the output of the third OR element is connected to the installation input of the counter of correctly performed operations and the information input of the counter of completed implementations, the output of which is connected to the input of the third comparison circuit, the second input of the readout permission of the unit of communication is connected to the output More than the first comparison circuit, the information input of the error counter, to the first input of the third OR element and The primary setup input of the adder, the second information input of which and the information input of the counter of correctly executed operations are connected to the output Not less than the first comparison circuit and to the first input of the first element AND whose output is connected to the second input of the first element OR, the single input of the first trigger is connected to the installation input error counter, with the input of the output of the adder and with the output of Equal to the third comparison circuit, 1377870 Connected to: the OR element, connected to you, and the output is populated to the second one of the register of the expansion of the remaining device and logic bots, it addresses the address of the second element and a quarter of the control position and the fourth elegenerator is incidental 20 Since you are here and there, you are not entering into me, but even until you have been able to do that, you are pulling you through nb, you are entering, and you are with and with you neither numbers, first, second and third registers, fourth and fifth comparison circuits, second and third triggers, first and second blocks of AND elements, fourth, fifth and sixth OR elements and a pulse shaper, with the output of the fourth OR element connected to the second inputs the third and fifth elements mHi and the second setting input of the adder, the first input of the fourth element OR is connected to the zero input of the third trigger and the output More than the second comparison circuit, the first group of information inputs of which is connected to the outputs of the second electric unit And, the control input of which is connected to the single output of the third trigger and the read input of the third register, the bit outputs of which are connected to the information inputs of the second group of the second comparison circuit by the output. Less than which is connected to the first input of the fourth And element, the output of which is connected to the second input of the first the AND element, and the second input of the fourth AND element is connected to the output of the Less than five comparison circuit, the output Equal of which is connected to the second input of the fourth OR element and to the zero input of the second three the one whose output is connected to the control input of the first block of elements And and to the read input of the second register, the bit outputs of which are connected to the information inputs of the second group of the fifth comparison circuit, the first group of information inputs of which are connected 12 o 0 0 5 5 five 0 five 0 With the outputs of the first block of elements AND, whose information inputs are respectively connected to the bit outputs of the counter of correctly performed operations and to the information inputs of the second block of elements Pi, the bit outputs of the micro-command address register are connected respectively to the address inputs of the microprogram memory block, and the input readout of the register of microinstructions addresses is connected to the single input of the second trigger and to the output of the More than a fourth comparison circuit, the first group of information inputs of which are connected respectively About the second day, the outputs of the first register, the second group of information inputs are connected respectively to the outputs of the second generator of uniformly distributed random numbers and the comparison resolution input of the fourth comparison circuit is connected to the output of the fourth delay element, the input of which is connected to the output of the second pulse generator, and the output of which is connected to the first input of the third element And, the second input of which is connected to the output of the first delay element, and the output of the third element And is connected to the first the read input of the microprogram memory unit and the first input of the sixth OR element, the second input of which is connected to the output of the More first comparison circuit, and the output of the sixth OR element is connected to the input of the second delay element, the read input of the first register and the start input of the second generator of uniformly distributed random numbers connected to the output of the pulse former, the input of which is connected to the output of zeroing the counter of the control position of the logic operation, the installed input of which is connected to the output of the fifth elec- The OR input, the first input of which is connected to the output More than the first comparison circuit, and the subtractive input of the control counter of the position of the logical operation is connected to the output of the second element AND, the first and second inputs of which are connected respectively to the output of the first element OR and to the output of the first element NOT connected to the single input of the third trigger and to the output of Not more than the fourth comparison circuit.