SU1405053A1 - Squaring device - Google Patents

Abstract

The invention relates to digital computing and can be used in the construction of specialized computing systems, functional transducers, information measuring systems and signal processing devices. The purpose of the invention is to reduce hardware costs. In this quadratic converter, a reduction in hardware costs is achieved by using a linear approximation of the original function, followed by a multiple correction of the difference between the original function and its approximation by approximating the correction functions with chords. The quadratic converter consists of a register 1, the first 2 and the second 3 adders, a memory block 4, -n switches 5.1-5.P, a group of elements NOT 6 with corresponding connections. 2 -il. Q in (L

Description

about

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The invention relates to digital computing and can be used in the construction of functional converters, specialized computers, information measuring systems, signal processing devices.

The purpose of the invention is to reduce hardware costs.

Figure 1 presents the structural scheme of the quad; Fig. 2 are diagrams for the operation principle.

The quadrator contains the register of 1 argument, the first 2 and the second 3 adders block 4 of memory, n switches 5.1-5.P, a group of 6 elements NOT. For example, integrated circuits K589IR12, K555IR22, K531IR22, etc. can be used as a register, K555IM65 K531IPZ as adders, 556PT4, 556PT5, etc. as a memory unit, K531LP5 as a memory unit, NOT - K531LN1.

The operation of the quad is based on the principle of internal approximation of the original function Y X, XsLO, l) with the organization of multiple recurrent correction of the difference between the original and its linear approximation by chords. Fig. 2a shows the original function Y X X and the approximating function Cf X. The difference between the functions cf and Y, the LL correction function (f-Y (Fig. 26), is also a quadratic function, also symmetric with respect to the axis, This means that dy can be similarly approximated by chords — functions (fig. 26). In turn, the difference / 1у 2 т V also acts as a corrective function and can be approximated by chords — functions (fig. 2c).

After the t-th step of the correction (FIG. 2d, a correction function 5 is obtained,

then the final transformation equation should be written

hi

Y (1: .-). one

The values of the correction function are stored in memory block 4 and serve to obtain an accurate conversion result. The analysis shows that E is a periodic function, symmetric on the period with respect to the period and

  2)

(2)

This means that when the input code X is equal to N, the volume of the memory block Q for storing values is determined by

(n, 1) .. (3)

From analysis (3) it follows that the number of chord correction steps must be chosen on the basis of the inequality

m.f- 1.

(four)

As follows from the diagrams (Fig. 2), the correction function C is, in general, is a periodic function with a period

2

T j -, which means: function i. can be reproduced in the first period, and in the following periods it is used due to the displacement along the X axis. In addition, since it is a symmetric function on the T period, it is sufficient to specify it on the interval O, y):

V., LH e o,).

(five)

To determine the values of V, on ing 1 2

in the interval yj, ug-), one can use expression (5), replacing 4X with

dX to y due to sims

(6)

From expressions (5) and. (6) it follows that in determining it is necessary to perform the operation of multiplying part of the argument by a factor of 2, where / is an integer. This means that the multiplication operation can be performed. By spatially shifting the argument bits to the right or left, depending on the sign of.

Thus, the operation of the switches 5.1-5, p is that, depending on the approximation area, they skip the values of the X part without changing or inverting, except for

In addition, at the inputs of the switches the spatial shift of the bits of the code X is carried out, i.e. a multiply operation is performed. The switch control is performed by the higher bits X. The number of switches n is determined through the number of correction steps as m + 1, since another switch is needed to control the memory block 4, in which the function values are stored, therefore

mu

n - 2 - if the accuracy of the quadrangular output of the first adder 2 forms the value Y x X according to the equation of the transformation (1).

Claims (1)

The formula of the shadow invented Quadrator containing the register of the argument, whose input is connected to the information input of the Quadrator, the first adder, whose outputs are the outputs of the Quadrator, the second adder, the memory block, n switches N (where ny - 2; N is the rank of the argument So, at the output of the second adder 3, the value of the sum of the correction functions is formed of all m 15 ment), the control inputs of which are connected to the outputs of the higher bits of the argument register, the remaining bits of which are connected to the information inputs of the n switchboards, you must have () j the 20 OD of the ri switch connected to the address the input of the memory block whose outputs are connected to the n-th group of inputs of the second adder, which is different from the fact that, in order to reduce hardware costs, the first group of inputs of the first adder is connected to the outputs of the register argument1 ten from y according to (1). The subtraction operation is organized by inverting the value at the output of the second adder 3 with the help of group 6 elements NOT and summing the inverted value of the sum of the correction functions with the value X in the first adder 2, while the transfer input of the adder 2 must be connected to the input of the logical 1. This means that X sum (n-1) -th of the second adder 30 is connected to the outputs of the switches from the first to (n-1) -th, and the outputs of the second adder through the elements of the NOT group connect with 2 - y., + an additional dinene with a second group of inputs of the first adder, the transfer input of which is connected to the input of a logical unit code, which is equivalent to the operation of the PI Zjb + from X, therefore, the quad about % V2% 2 / t d y21t-1) 2 Compiler A.Litvin Editor V.Petrash Tehred M.Didyk Proofreader G.Reshetnik Order 3106/53 Circulation 704Subscription VPI-SHI USSR State Committee for inventions and discoveries 13035, Moscow, Zh-35, Raushsk nab., 4/5