SU1097994A1 - Device for transforming binary code to code of number system with negative radix - Google Patents

Abstract

1. A device for converting a binary code into a negative base number system code, containing an AND element, characterized in that, in order to expand the field of application of the device due to the possibility of converting negative binary numbers in the forward code, the device contains a one-bit adder, two a delay element and a clocking node, the information input of the device being connected to the first input of a one-bit adder, the output of the sum of which is connected to the first input of the AND element and the device output The output of the element And through the first delay element is connected to the second input of the one-digit adder, the transfer output of the single-digit adder through the second delay element is connected to the third input of the single-bit adder, the device clock input is connected to the formational input of the clock unit, the sign input of the device is connected with the control input of the clocking node, the output of which is connected to the second input g of the element I. co.

Description

2. A device for converting a binary code into a negative base number system code, which contains an AND element, characterized in that, in order to expand the field of application of the device by providing the possibility of converting negative binary numbers in the forward code, the device contains a half adder, an OR element, the delay element and the node clocking, and the information input device is connected to the first input of the half-adder, the output of the sum of which is connected to the first input of the element And the device output, the output element This AND is connected to the first input of the OR element, the second input of which is connected to the transfer output of the half adder, the output of the OR element is connected to the second input of the clock input node, the sign input of the device is connected to the control input of the clock node whose output is connected to the second input of element I.

3. The device according to PP. 1 and 2, characterized in that the clocking node contains a trigger and a switch, the output of which is connected to the node output, the information inputs of the switch are connected to the forward and inverse outputs of the trigger, the counting input of which is connected to the information input of the node, the control input of the node is connected to Let's switch input.

one

The invention relates to digital computing and can be used in computer arithmetic devices operating in number systems with negative bases.

It is known that any number A mop

Can be represented as A .L.fc-6

where B -1 and O 4 b .SLike

the representation of numbers allows the recording of positive and negative numbers without a special indication of the sign. The execution of arithmetic operations in this case consists only in actions on the numbers proper, no operations on signs are performed, which simplifies the execution of arithmetic operations 1.

Devices operating in a negative base number system may operate in conjunction with conventional binary equipment, and IT requires the transfer of numbers from one number system to another. This task can be solved programmatically. 2

However, this is not always convenient, since it requires the use of universal computers.

The closest to the proposed technical entity is a device for converting a binary code into a number system code with a negative (minus-binary) base, containing two flip-flops, AND, AND-NOT, NOT elements, with the counting input of the first flip-flop trigger, with a clock input of the device, the information input of which is connected to the first inputs of the first element I. and the first element NAND and to the input of the element NOT, the output of which is connected to the first inputs of the second element AND the second element and NAND, the direct and inverse outputs of the first trigger are connected to the second inputs of the first and second ele ments, respectively, whose outputs are connected to the installation inputs of the second trigger, the direct and inverse outputs of which are connected to the second inputs of the second and first AND elements accordingly, the outputs of which are connected to the inputs of the third NAND element, the output of which is the output of the device Csj. The disadvantage of this device is a small area of application, since it is intended to convert binary numbers into additional code. If the binary numbers are negative and are represented in the direct code, then a direct code to auxiliary converter will be used and vice versa, which approximately doubles the equipment and reduces the speed. The purpose of the invention is to expand the field of application of the device by providing the possibility of converting binary numbers into a direct form. This goal is achieved by the device for converting a binary code into a system code. A negative base number containing the AND element contains a one-bit adder, two delay elements and a clock node, the device information input connected to the first input of the single-digit adder, the sum output of which is connected to the first input of the AND element and the device output, the output of the AND element through the first delay element is connected to the second input of the single-digit adder, the transfer output of the single-digit adder through the second delay element is connected to the third input of the single-digit sum of the matrix, clock the input of the device is dinin with the information input of the clocking node; the sign input of the device is connected to the control input of the clocking node whose output is connected to the second input of the element; In addition, the device for converting the binary code into the number system with a negative base, containing the And element, contains a half-adder, an OR element, a delay element and a clocking node, with the information input of the device connected to the first input of the half-sum of the mator, the output of which is connected to the first input of the AND element and The output of the device, the output of the AND element is connected to the first input of the OR element, the second input of which is connected to the transfer output of the half accumulator, the output of the OR element through the delay element is connected to the second input of the half accumulator, the clock input of the device is connected to the information input of the clock node, the sign 44 input of the device is connected with the control input of the clocking node, the output of which is connected to the second input of the element I. The clocking node contains a trigger and a switch, the output of which is connected to the output of the node, information inputs The switches are connected to the forward and inverse outputs of the trigger, the counting input of which is connected to the information input of the node, the control input of the node is connected to the control input of the switch. FIG. 1 shows a first embodiment of the deviceJ in FIG. 2 shows a second embodiment of the device; FIG. 3 shows an example of a clocking assembly; in fig. 4 is another example of clocking node execution. A device for converting a binary code into a code of a number system with a negative base in the first embodiment (FIG. 1) contains a one-bit adder 1, an AND element 2, delay elements 3, 4 and a clock node 5. The information input 6 of the device is connected to the first input of the adder 1, the output of the sum of which is connected to the output 7 of the device and the first input element And 2, the output of which is connected to the input of the delay element 3. The transfer output of the adder 1 is connected to the input of the delay element 4. The outputs of the delay elements 3 and 4 are connected to the second and three im-input adder 1, respectively. The sign input 8 of the device is connected to the control input of node 5, the information input of which is connected to the clock input 9 of the device, and the output to the second input of the I 2 element. A device for converting binary code into a number system with a negative base according to the second variant (FIG. 2) contains a half-adder 10, an element AND 2, an element OR 11, a delay element 3 and a clock unit 5. Information input 6 of the device is connected to the first input of the half-adder 10, the output of the sum of which is connected to the output 7 of the device and to the first input element I 2, the output of which is connected to the first input of the element OR 1i, the second input of which is connected to the transfer output of the half-adder 10, the output of the element OR 11 through the delay element 3 is connected to the second entrance of the half-adder to. The sign input 8 of the device is connected to the -control input of node 5s whose information input with clock input 9 is connected to the output and to the second input of element II 2. The clock node 5 is designed to skip depending on the sign of the convertible only odd clock number impulses from a series of pulses, from which are delivered in accordance with the ocher /. discharge convertible number-gsh i input to the device in a sequential form. The execution of the node S can be very diverse. For example, as shown in FIG. 3j, node 5 contains a trigger 12 to switch 13, the output of which is node 5, the control input is connected to the control input of node 5 (connected with the device 8) S and information inputs are connected to direct and inverse diagrams of trigger 12, the counting input is connected to the information input of node 5 (connected to input 9 of the device), KoMi syTaTop 13 can be, for example, performed on I lAj 15s and MI 16 elements (it can be done in this way and differently, for example on logical elements of another type Trigger 12 before starting work, it zeroed the signal, arriving at its installation input. Node 5, so configured, can be impregnated if j the signal on; 1stuple 8 is potential (kept constant throughout the device operation time), the signal at input 8 is pulse, node 5 can be connected to trigger 17, the direct output of which is the output of node 5. The counting input is connected to the information input of node 5 (input 9) s whose control input (input 8) is connected to the installation input of the trigger 17 carried out full installation of a trigger. The device works as follows. In the first variant, in the case of converting positive numbers, node 5 delivers the enabling signal to the second input of the AND 2 element to the even operation of the device, 5 t, e, to those 46, when the input 6 receives even numbers d convertible binary code. The converted binary number in the direct code should be represented by n (t + 2) bits, where t is the number of binary bits., Which provides the dynamic range of the converted binary numbers. With the chosen circuit implementation of node 5, the clock signals arriving at input 9 must somewhat outpace the corresponding information signals at input 6 so that by the time the signal appears at the output of the sum of adder I, the transients in node 5 are already completed and the AND element 2 was endowed closed (or open) at the second input, while in the case of the presence of 1 at the output of the sum of adder 1 (in even clock) it passes through the open element AND 2 to the input of the delay element 3, from the output of which it arrives at second The input of adder 1, In the case of formation of 1 at the output of transfer of adder 1, it, being delayed for one clock (delay element 4), arrives at the third input of adder 1. We will show the conversion process using the example of converting the binary code C 00111 to the number system code negative basis. In the first cycle of operation, the value 1 of the low-order code C, which enters the input of the adder 1, passes to its output, and therefore to the output 7 of the device. Element And 2 in the first cycle is closed by the absence of a permissive signal at the output of node 5. In the second cycle, the value 1 of the second bit of code C (the numbering of the bits comes from the younger) also arrives at output 7, however, since the output of node 5 is resolving the signal, this value, in addition, passes to the input of the delay element 3, which memorizes it before the start of the next (third) cycle. In the third cycle, the values 1 arrive at both the first and second inputs of the adder 1. At the same time, the value O is formed at the output of the adder 1 (which arrives at the output 7, and the value 1 at the transfer output, which is stored by the delay element 4 until the beginning of the fourth tact). In the fourth cycle, the first and second inputs of the adder 1 receive the values O, and the third input (from the output of the delay element 4) receives the value 1. The output of the sum of the adder 1 forms the value 1, which arrives at the output 7 of the device and through the open element And 2 (since the output signal of the node 5 in the fourth clock cycle is the enable signal) - to the input of the delay element 3. In the fifth clock cycle, the value 1 from the output of the delay element 3 arrives at the second input of the adder 1, forming at its output a sum of 1, which goes to output 7. Thus, at output 7 For the three cycles, code A 11011 is formed, which is the representation of code C in the number system with a negative base of B--2 (A (-2) AND - (- 2Y + (-2) -0 h +) (- 2) 1 + (-2) - 1 16 -8 + 0-2 + 1 7; C + + + + 2.1 + 2-1 0 + 0 + 4 + 2 + 1 7). When converting negative numbers, the operation of the device is similar to that described above, with the only difference that the supply of the enabling signal at the output of the node 5 takes place in certain cycles of operation of the device. In the second variant (Fig. 2), the logic of operation is essentially the same. Node 5 functions identically as shown in the first embodiment, the output signals only in the even ticks of the device when converting positive numbers (O value at input 8) or only in the odd device ticks when converting negative numbers (value 1 at input 8 ) 1 is fed to one of the inputs of the element OR 11 either in the case of the occurrence of signal 1 at the output of the sum of half adder 10 at the time when the output of node 5 has an enabling signal, or in the case of the occurrence of signal 1 at transfer output along usummatora 10. The logic device eliminates the occurrence of simultaneous signals 1 on both inputs of the OR gate 11. In the case of the occurrence of one signal in one of the OR 4, it passes the inputs to the input of the delay element 3, which performs its storage before the next stroke. The half-adder 10 sequentially converts the bits of the binary code, starting with the youngest, as follows. If in the previous clock the input 1 of the delay element 3 did not receive the signal 1, this bit of the code being converted passes to the output 6 without changing; if, in the previous clock, input 1 of the delay element 3 received a signal 1, this bit of the code being converted is inverted. Thus, the proposed device with a small amount of equipment allows the conversion of a binary code into a number system with a negative base. Compared with the prototype, this device allows the conversion of both positive and negative numbers given by the direct code (without first converting the direct code to the additional one), which in this case allows the device to expand its scope. In its implementation, the second option, with a slight increase in the tact of operation, requires a smaller amount of equipment and is preferred.

Rig.Z

2

Claims (1)

1. A device for converting a binary code to a number system with a negative base, containing the And element, characterized in that, in order to expand the scope of the device by making it possible to convert negative binary numbers in direct code, the device contains a single-bit adder, two a delay element and a clock node, the information input of the device being connected to the first input of a single-bit adder, the sum output of which is connected to the first input of the AND element and the device output , the output of the element And through the first delay element is connected to the second input of the single-bit adder, the output is the transfer of the single-bit adder through the second delay element is connected to the third input of the single-bit adder, the clock input of the device is connected to the information input of the clock node, the sign input of the device is connected to the control input the clock node, the output of which is connected to the second input of the element I.