SU1394395A1 - Analog multiplier - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the accuracy of multiplication. The device contains seven bipolar transistors (T) 1-7, resistors (P) 8 and 9, current sources (IT) 10 and 11, differential. cascade 12. In the absence of a signal at the inputs of the signals of the first and second factors, the currents flowing through T 1 and 2 are equal to each other up to the consistency of P 8 and 9 by means of the neg. feedback through T 5 and 6 and their sum is equal to the value of current IT 11. The currents flowing through T 3 and 4 are also equal and their sum is equal to the value of current IT 10. When a signal appears, feedback through T 5 and 6 provides equality of currents through P 8 and 9. T 7 performs a negative. feedback on common mode input. The accuracy of multiplication is not affected by the base currents T 1 and 2, which provides an increase in the accuracy of multiplication. 1 il. and s

Description

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The invention relates to the field of radio engineering and communications and can be used in computing.

The purpose of the invention is to increase the accuracy of multiplication.

The drawing shows a structural electrical circuit of an analog multiplier.

The analog multiplier contains the first, second, third, fourth, fifth, sixth and seventh bipolar transistors 1-7, the first and second relays

 is the current at the signal input in the pogo multiplier of the analog multiplier. Thus, an analogue commutator allows to multiply the currents 1, 1, 1, 1 vhz to divide the result by

zistors 8 and 9, the first and second sources - 5 I. For the accuracy of multiplying NICKY 10 and 11 of the current and the differential stage 12.

Analog multiplier works as follows.

The base currents of the first and second bipolar transistors 1 and 2 do not affect either, which ensures the accuracy of the multiplication.

20

In the absence of a signal at the inputs of the signals of the first and second multipliers of the analog multiplier, the currents flowing through the first and second bipolar transistors 1 and 2 are equal to 25 each other up to the consistency of the first and second resistors 8 and 9 due to the effect of negative feedback through the fifth and the sixth bipolar transistors 5 and b and 30, their sum is equal to 1 current value of the second current source 11, and the currents flowing through the third and fourth bipolar transistors 3 and 4 are also equal to each other, and their sum is equal to 35 current n The first current source 10 When a signal at the inputs of the signals of the first and second factors of the analog multiplier feedback through the fifth and sixth 40 bipolar transistors 5 and 6 ensures the equality of the currents through the first and second resistors 8 and 9, and thus the difference currents of the first and

Claims (1)

Claims of the invention: Analog multiplier comprising a differential stage, the first, second, third, fourth, fifth, sixth and seventh bipolar transistors, the first and second resistors, the first and second current sources, the emitters of the first and second bipolar transistors being combined, the first the differential input of the differential cascade is connected to the base of the first bipolar transistor and to the collector of the third bipolar transistor; the second differential input of the differential cascade is connected to the base of the second bipo and with the collector of the fourth bipolar transistor, characterized in that, in order to increase the accuracy of multiplication, the collectors of the fifth and sixth bipolar transistors are combined and connected to the output of the first current source and to the base of the seventh the second bipolar transistors 1 and 2d5 of the bipolar transistor, the emitter is equal to 1 in 1, g. (ъх 1.1 difference of currents at the input of the signal of the first multiplier of the analog multiplier). The seventh bipolar transistor 7 performs negative feedback on the common-mode input signal. Then the voltage difference between the bases of the first and second bipolar transistors 1 and 2 is equal to 50 the second emitters of the fifth and sixth bipolar transistors are connected to the collectors of the third and fourth bipolar transistors, the bases of which are combined and connected to the emitter point of the first and second bipolar transistors, the third and fourth emitters bipolar transistors are combined and connected to a common bus, the second current source is connected between the point of connection of the bases of the third and fourth bipolar transit, ,, arcth J- - -, 4i where the temperature potential of the pn junction. It depends on the input currents of the differential stage 12. The difference of the currents / II g, at the output of the analog multiplier is equal to ,and" 1 bxi  exe th () i- i -al t -eleven X 1, 7 where i  - The current at the signal input of the second multiplier of the analog multiplier. Thus, the analog multiplier allows the multiplication of currents 1, 1, 1, 1 vhz to divide the result by current I. On multiplication accuracy current I. On multiplication accuracy neither the base currents of the first and second bipolar transistors 1 and 2 are affected, which ensures an increase in the multiplication accuracy. Claims of the invention: Analog multiplier comprising a differential stage, the first, second, third, fourth, fifth, sixth and seventh bipolar transistors, the first and second resistors, the first and second current sources, the emitters of the first and second bipolar transistors being combined, the first the differential input of the differential cascade is connected to the base of the first bipolar transistor and to the collector of the third bipolar transistor; the second differential input of the differential cascade is connected to the base of the second bipo and with the collector of the fourth bipolar transistor, characterized in that, in order to increase the accuracy of multiplication, the collectors of the fifth and sixth bipolar transistors are combined and connected to the output of the first current source and to the base of the seventh bipolar transistor, the emitter is the second emitters of the fifth and sixth bipolar transistors are connected to the collectors of the third and fourth bipolar transistors, the bases of which are combined and connected to the point of connection of the emitters of the first and second bipolar transistors, the emitters of the third and fourth bipolar pn transistors are combined and connected to a common bus, the second current source is connected between the point of connection of the bases of the third and fourth bipol transit313943954 the sides and the common bus at the second output base of the fifth bipolar transistor of the first resistor are connected to the collection and the second output of the second resistor with a torus and base, respectively, the first base of the sixth bipolar transistor and the first bipolar transistors, jpa are the input of the signal of the second second end of the second The analog multiplier connection resistor is multiplied with the collector and with the base of the respective bodies; the common-mode input of the second and sixth bipolar cascade is the input of the transistor signal, and The second factor is the analog re-output of the first resistor from the multiplier.