SU1316089A1 - Analog-to-digital converter - Google Patents

Description

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The invention relates to automation and information-measuring technology and can be used in systems for collecting analog information intended for the automation of technological processes and scientific research.

The purpose of the invention is to improve the accuracy of conversion and the extension of the field of application due to the possibility of converting different polarized, rapidly changing signals.

In Fig.1, a functionalized analog-to-digital converter circuit is introduced; Fig. 2 is a functional block diagram of the formation of the reference signal; FIG. 3 is a functional block diagram of the address selection of the conversion channel; Fig. 4 is a functional block diagram of the control unit.

The analog-to-digital converter (Fig. 1) contains n storage sampling units 1.1-ln, n units 2.1-2.P formation, reference signal, n keys 3.1-Z.p and additional keys 4.1-Dn, integrator 5, comparator 6, the source 7 of the reference voltage, the block 8 address selection channel conversion, block 9 control

The unit 2 of the formation of the reference signal (Fig. 2) is implemented on two charging keys 10.1 and 10.2, four keys 11.1-11.4 of the choice of polarity, Analog storage element, made in the form of a capacitor. 12,

Block 8 of the address selection of the conversion channel (FIG. 3) is performed on three blocks 13-15 of the AND elements, the distributor 16 pulses.

The control unit 9 (FIG. 4) is executed on an inverter 17, seven elements AND 18-24, two pulse makers 25 and 26, two elements OR 27 and 28, a clock generator 29, a frequency divider 30, four triggers 31-34,

Analog-to-digital converter works as follows.

There are two possible modes of operation of the analog-digital converter: the conversion of n independent input signals and the conversion of a single signal.

Consider the first mode. The main disadvantage of integrating A1SCs is the limited speed, as a result of which limitations are imposed both on the number of independent signals being converted and on the speed of 60892

the rate of change of these signals. The use of sampling-storage schemes partially eliminates this limitation. However, with a large number of input channels, the storage capacitance begins to affect the storage mode, which naturally leads to an error in the analog-digital conversion,

o Eliminating these limitations allows the introduction of additional storage capacity with the appropriate keys for each of the n conversion channels. At the beginning of the conversion, the triggers 31-34 and the frequency divider 30 of the control unit 9 are set to the zero state. The pulses from the generator 29 through the element 22 and the element OR 28 are fed to the distributor 16 pulses of block 8, and the pulses of the distributor 16 to the inputs of blocks 1 and the first control inputs of blocks 2 of all channels,

As a result, blocks 1 are charged

5 input signals and signals up to the value of Ugy,, 2, ..., n, and capacitors 12 to the value of U, where Ug is the source voltage 7. After interrogating all the channels, the last pulse

30 of the distributor 16 through the element AND 24 switches the trigger 33 to one state, the element 22 and closes, the trigger 34 also goes to 1, and the ADC goes to the input conversion mode

35 beeps. Since the distributor 16 has a Ring structure, it automatically returns to the first position. At the same time, the rate of polling channels is not less than 1 / (T), where T, 40 is the integration time; atsc is the maximum duration of the output pulse of the converter corresponding to the maximum value of the input signal.

45 Element And 21 is opened by a signal from a single output of the trigger 33, and pulses are received at the frequency divider 30, the division factor of which determines the integration time T

0 generator 29, the First pulse from the element And 21 sets the trigger 32. in one state, which is maintained until the output pulse of frequency divider 30 appears. Impulse with

55 of the first position of the distributor 16 opens the first of the elements AND block 15, closes the key 3.1, the voltage stored n; it is in the block 1.1, goes to the integrator 3. The value of the voltage potential leakage is equal to

-t / Tp.

1 Learn

- where T

and. ,, e

flJ h

, 2,

P

. pi is the constant discharge capacitance in block 1.1 of the 1st channel. If the integrator 5 has a negative output signal, the voltage at the output of the comparator 6 is logic level 1, if positive, the logic level is O. In the first case, the signal from the output of comparator 6 is fed directly to the first input of the element And 18, in the second through the inverter 17 to the first input element 19. After the end of T, the output of splitter 30 of frequency, trigger 32 is set to O, and trigger 31 is set to 1, and the corresponding high potential is applied to the second inputs of elements 18 and 19, as well as to the input of element I 20, simultaneously with It closes the element AND 21, one of the inputs of which is connected to the zero output of the trigger 31. As a result, a high potential appears depending on the polarity of the input signal at the output of either element 18 or element 19, with the corresponding pairs opening. the polarity selection keys 11 from the output of the corresponding block 1.

Switching the trigger 31 to 1 opens the valve 20, through which the pulses of the generator of the clock pulses 29, simultaneously turn on the corresponding valve from group 14, which closes a certain key 4. As a result, a capacitor 12 is connected to the input of the integrator 5, and living

and; Uoe

-t / t

Ro

1 1.2p.

According to the known relations describing the operation of the push-pull integrating time of the pulse converter, the duration of the output pulse is determined by -TI / TP,

K Y

Ur

T

 and

-YY, + 7) / Tro5

To const

provided

oi,

what

t,

R;

+ g "

Di t. + G,

to rm- -)

and,

(one)

 po

Uo

T „e

.

PCI

AND

considering that T T

poi

- KT

- and-and;

five "

Thus, ideally, the leakage of capacitors in blocks 1 does not affect the measurement accuracy. In real terms, T p; Tr, - full compensation is not achieved, however, the error due to leakage of capacitors in blocks 1 can be reduced. From relation (1), the exponent indicator can be represented as

- T t and p

, -) / t

(TI, T poi

R;

 Ro

since t "t

5 then (T po; - Tr, -) / Tr, T

rank Tr; Tr ,.

/ (t

POi

poi VeliPOi

- T,

ECV

0

five "

five

0

five

0

five

can be considered as the equivalent time constant of the capacitors in the blocks. It is not difficult to see that.

Since the memory error is determined by the constant discharge of the storage capacity, an increase in this constant reduces the corresponding level of error. When the voltage at the output of the comparator 6 becomes equal to zero, one of the elements 18 or 19 is closed, the falling edge of one of the drivers 26 or 25 is triggered. The output pulse of the driver 26 (25) through the element OR 27 goes to the R input of the trigger 31, which switches to the O state, the AND element 20 is closed. The number of pulses passed through this valve is proportional to the measured signal of the 1st channel. The voltage drop caused by switching the trigger 31, through the OR 28 element, switches the distributor 16 to one position and begins the conversion of the signal of the next channel. After polling all 12 channels, the pulse from the last cell of the distributor through the element And 23 switches the triggers 33 and 34 to the zero state, and the element 21 simultaneously closes. Thus, the whole circuit returns to the original cocTOHHiie.

In the single signal conversion mode, all the analog signal circuits are combined and connected to the source of the signal being converted. The converter works in the same way as the previous mode.

Claims (4)

1. An analog-to-digital converter containing p keys, where n is the number of input convertible signals whose outputs are combined, and the control inputs are connected to the corresponding first outputs of the block of the address block for conversion channel selection, the first input of which is connected to the first output of the control unit, the first input which is connected to the comparator output, two additional keys, the outputs of which are combined, and the control inputs are connected to the corresponding second outputs of the block of the address conversion channel selection, I distinguish In order to increase the accuracy of conversion and expand the scope of application due to the possibility of converting differently changing rapidly changing signals, a reference voltage source, n 2 additional keys, an integrator, n blocks of formation of reference signals, n sample-selector blocks, analog the inputs of which are input currents of the corresponding conversion channels, the outputs are connected to the analog inputs of the corresponding n keys, the control inputs are combined with the first control inputs of the corresponding Formation p blocks of formation of reference signals and connected to the corresponding third outputs of the block of address selection of the conversion channel, the corresponding second outputs of which are connected to the corresponding control inputs of p-2 additional keys, the fourth output connected to the second input of the control unit, outputs from the second to the fourth of which are connected respectively, to the inputs from the second to the fourth block of address selection of the conversion channel, the fifth output is the output bus, and the pin and the seventh outputs are connected The second and third control inputs are respectively - n blocks of forming reference signals, the first analog inputs of which are combined and connected to the first output of the voltage source, the second analog inputs are combined and connected to the second output of the voltage source, outputs are connected to the analog inputs the corresponding n additional keys, the outputs of the n-2 of which are combined with the output of the first additional key and connected to the first input of the integrator, to the second input of which is connected the output ne out of JO n keys, the integrator output is connected to the first input of the comparator, the second input of which is connected to the zero potential bus. 2. The converter according to claim 1, T is characterized in that the unit for generating a reference signal is made on the first and second charging keys, the first, second, third and fourth polarity selection keys, an analog storage element made in the form of a capacitor, the first the output of which is combined with the output of the first and analogue input of even the polarity selection keys and connected to the output of the first charging switch; the second output of the capacitor is combined with the output of the second and analogue inputs of the third polarity selection keys and Exit second charging key, the control input of which is combined with the control input of the first charging switch and is the first control input of unit 25 forming the reference signal, the analog inputs of the first and second charging keys are the first and second analog inputs of the reference signal generation unit, respectively, while the analog inputs of the first and second polarity selection keys are combined and connected to the zero potential bus, the outputs of the third and fourth the polarity selection keys are combined and are the output of the reference signal generation unit, the control inputs of the first and third polarity selection keys are combined and are the second control the input of the reference signal generating unit, and the control inputs of the second and fourth polarity selection keys are combined and are the third control input of the unit for generating this single signal. 3. The transducer according to claim 1, T is characterized in that the block of address selection of the conversion channel is made on the first, second and three blocks of AND elements and the pulse distributor, whose input is in the first input of the block of address selection of the conversion channel, n outputs are connected to the corresponding 55 inputs of the first groups of inputs of the first, second and third blocks of elements AND whose outputs are the corresponding first, second and third outputs of the canal 3540 JO 15 The transformations, the inputs of the second groups of inputs are combined respectively in the first, second and third blocks of the AND elements and are the second, fourth and third inputs of the address block of the conversion channel, respectively, while the n + 1 output of the pulse distributor is the fourth output of the address select a conversion channel. 4. The converter according to claim 1, characterized in that the control unit is made on a clock pulse generator, seven AND elements, two pulse formers, two OR elements, a frequency divider, four triggers, an inverter whose input is combined with the first input of the first AND element and it is the first input of the control unit, and the output of the sub-20 keys to the first input of the second element I, the output of which is the seventh output of the control unit and connected to the input of the first pulse generator, the output of which is connected to the first input of the first the OR element, the output of which is connected to the setup input to the zero state of the first trigger, the second input is connected to the output of the second pulse shaper 30, the input of which is connected to the output of the first AND element and is the sixth output of the control unit; the second input of the first And element is combined This AND, the first input of the second OR element, the first input of the third AND element, is connected to the forward output of the first trigger and is the fourth output of the control unit, the inverse output 40 25 the first trigger is connected to the first input of the fourth element I, the clock input is the third output of the control unit and connected to the forward output of the second trigger, the setup input to the zero state of which is connected to the output of the frequency divider, and the setup input into the single state is combined with the input frequency divider and connected to the output of the fourth element And, the second input of which is combined with the second input of the third element And, the output of which is the fifth output of the control unit, with the first input of the fifth element And and connected n to the output of the clock pulse generator, the third input of the fourth element I is connected to the forward output of the third trigger, the setup input to the zero state of which is combined with the setup input to the zero state of the fourth trigger and connected to the output of the sixth element I, the first input of which is combined with the first input of the seventh element And is the second input of the control unit, the second input is connected to the forward output of the fourth trigger, the inverse output of which is connected to the second input of the seventh element And, the output of which chen entry to installation in a single state of the third flip-flop, which inverted output is the second output of the control unit and a second sub-input of the second elements 35 the key to the clock input of the fourth the trigger and the second input of the fifth AND element, the output of which is connected to the second input of the second OR element, the output of which is the first output of the control unit. five 0 0 five the first trigger is connected to the first input of the fourth element I, the clock input is the third output of the control unit and connected to the forward output of the second trigger, the setup input to the zero state of which is connected to the output of the frequency divider, and the setup input into the single state is combined with the input frequency divider and connected to the output of the fourth element And, the second input of which is combined with the second input of the third element And, the output of which is the fifth output of the control unit, with the first input of the fifth element And and connected n to the output of the clock pulse generator, the third input of the fourth element I is connected to the forward output of the third trigger, the setup input to the zero state of which is combined with the setup input to the zero state of the fourth trigger and connected to the output of the sixth element I, the first input of which is combined with the first input of the seventh element And is the second input of the control unit, the second input is connected to the forward output of the fourth trigger, the inverse output of which is connected to the second input of the seventh element And, the output of which chen entry to installation in a single state of the third flip-flop whose inverse output is WTO (pur. 2 / j & & W (rig 5 / " fS at & B & & & &