SU1406792A1 - Device for measuring analog values with automatic scaling - Google Patents

Abstract

The invention relates to a pulse technique and can be used in information measuring systems for measuring analog values in a wide range with automatic scaling. The invention makes it possible to extend the field of application by measuring pulsed voltages. This is achieved in that the device containing the scaler 1, the scale selector 2, the 3 pulse distributor, the AND 4 element, the 5 sync pulse generator, the analog-to-digital converter 6, executed on the zero-organ 7, the digital-analog converter 8, block control 9, element 17 EXCLUSIVE OR, element AND-NOT 18, element NOT 19, element AND 10, generator AND clock pulses, one-shot 12, sampling and storage unit 21, multiplexer 22, voltage follower 23, mode selector 24, selector 25 clock pulses, register 20 follow solitary approximations, the element is NOT 26, the D-trigger is 27. 4 Cp f-crystals, 7 ill. i U)

Description

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The invention relates to a pulse technique and can be used in information measuring systems for measuring analog values in a wide range with automatic scaling.

The aim of the invention is to expand the scope of use by

The selector 25 sync pulses (FIG. 6) contains an EXCLUSIVE OR element 46, an NOT 47 element, a delay element 48, an EXCLUSIVE OR element 49 and 50, an RS-flip-flop 51, D-flip-flops 52 and 53 and the elements 54 and 55 EXCLUSIVE OR.

The control block 9 (FIG. 7) consists of a D-flip-flop 56, elements OR

making it possible to measure NOT 57 and 58, n elements 59 EXCLUSIVE OR, where n is the number of bits of the ADC.

The device works as follows.

When a signal is applied to the input bus- 15, the one-shot 12 is triggered.

(Fig. 25) and the device is reset.

The impulse from the output of the one-shot 12 (FIG. 2U together with the pulses of the generalized pulses.

1 shows a functional diagram of the device; 2 shows diagrams of operation of the device in the mode of measuring DC voltages; Fig. 3 shows diagrams of the device operation in the mode of measuring pulse voltages; 4 is a functional block diagram of the sample and hold unit; in Fig. 5, a functional diagram of the mode selector 1 1 (Fig. 2a) enters the selector; Fig. 6 is a functional diagram 24, where after the completion of all transition-selector clock pulses; Fig. 7 is a functional block diagram of the control unit.

The device (Fig. 1) contains a scale measuring block 25 1, a selector 2 of the scale, a distributor of 3 pulses, an element 4, a generator of 5 sync pulses, an analog-to-digital converter ii (ADC) 6 in a counterbalanced counter-Q

processes in block 1, a start pulse is formed (fig. 2b). The pulses from the output of the one-shot 12 (figure 2) and Start enter the selector 25, where the ADC clock pulses are generated (Fig. 2-2,3). At the same time, by pulse, the ADC setting (Fig. 22.) register 20 and block 9 are reset and N 0.11 ... code is set at the inputs of DAC 8, and voltage 0 is set at its inputs (FIG. 2AA) .

NIN, including a serially connected zero-body 7, a digital-to-analog converter, an inverter (DAC) 8 and a control block 9, a series-connected element 10 and a clock generator 11, one-shot 12, input buses 13 and 14, output buses 15 and 16, element 17 EXCLUSIVE OR, element NAND 18, element NOT 19, sequential approximation register 20, block 21 of sampling and storage, multiplexer 22, voltage follower 23, mode selector 24, selector 25 sync pulses, element 26, trigger 27 and input bus 28.

In the time diagrams (FIGS. 2 and 3), the letters 0.5, b, g, 9 ,,, and,, p, p, c, denote the voltages in accordance with the 1st points of the circuit in FIG. 7

Sampling and storage unit 21 (Fig. 4) contains a peak detector 29, a dual comparator 30, elements HE 31-33, D-triggers 34 and 35, element I 36, source 37 of threshold voltages.

The mode splitter 24 (FIG. 5) consists of a single vibrator 38, a frequency divider 39, a pulse counter 40, a HE 4 element, a multiplexer 42 of the OR 43 and 44 elements, a D-flip-flop 45.

BIG OR OR, where n is the number of bits of the ADC.

The device works as follows.

When a signal is applied to the input bus 14, the one-shot 12

(Fig. 25) and the device is reset.

The pulse from the output of the one-shot 12 (Fig. 2U, together with the pulses of the generator 1 1 (Fig. 2a) goes to the selector 24, where after the completion of all the transition

processes in block 1, a start pulse is formed (fig. 2b). The pulses from the output of the one-shot 12 (figure 2) and Start enter the selector 25, where the ADC clock pulses are generated (Fig. 2-2,3). At the same time, by pulse, the ADC setting (Fig. 22.) register 20 and block 9 are reset and N 0.11 ... code is set at the inputs of DAC 8, and voltage 0 is set at its inputs (FIG. 2AA) .

Pulse Start (Fig. 2b) ends the pulse of the ADC setup (Fig. 22). After that, the second ACh1 clock pulse (Fig. 29) is formed in the selector 25, which determines the sign of the measured voltage with respect to its positive front. At the same time, the inputs of the block 9 receive the Poll of the null-organ (Fig. 1, 2), the Strobe sign (Fig.1, 2e) and the signal from the output of the null-organ 7.

Voltage U comes from block 1 through multiplexer 22 (Fig. 2A), repeater 23 to the null organ 7. As a result, the signal O appears at the output of the null organ 7, and at the first input of the DAC B signal 1. These signals arrive the element 17, at the output of which the signal 1 appears. As a result, since the inverting output of the D-flip-flop 27 sends a signal 1 to the other input of the IS-NE 18 element, the signal O appears at the output of this element, 19 signal 1 (FIG. 2k). At the same time at the inputs of the DAC 8 code is set

I, 1 1 ... I, a is a voltage at its output (s ". If this is UU, then the output of element 18 will be a signal O, and the output of element 19 (Fig. 2k) is a signal 1, the opening element And A. As a result, a positive differential from element 26, corresponding to the pulse start pulse, starts generator 5 and then the scale switches in block 1. After all transients associated with switching and scaling, the selector 24 gives the next start pulse (Fig . 2 B) and, if Uy 7 U, then generator 5 is triggered again and the next switching occurs scaling limit. If now after scaling and.;

7 switches to state 1. A signal O appears at the output of element 17, a signal I appears at the output of element 18, and a signal O appears at the output of element 19 (Fig. 1, 2, k), which closes element 4. by the arrival of a positive differential from switch element 26, D-trigger 27 supplies the enable potential (Fig. 2g to element 10, which sends clock pulses from generator 11 to selector 25. Signal from the output of D-trigger 27 (Fig.) simultaneously enters the selector 24 and prohibits the formation of a pulse Start. In this case, from the selector 25 to the input of block 9 (FIG. 1,

2d) clock pulses are received Poll of the null organ, as well as clock pulses shifted by the duration of one clock pulse (due to the time of voltage setup in the DAC 8) clock pulses (Figs 1.23), fed to the input of A1D11 6.

As a result, conversion to ADC 6 takes place. Scale and transform results are output from units 15 and 16. If U) (negative polarity, i.e. | UI / Scd I, then after setting A1D1 to its initial state, when block 9 outputs to the DAC inputs 8 O, I 1 ... 1, and the output of the PAP 8 sets the voltage l; j, n 0) with the arrival of the second ADC clock (Fig. 23) by its positive difference at the outputs of the control unit by a signal from the zero organ 7 0.00 ... This efficiency is set at the output of the DAC

A voltage equal to K,. Wherein

0

five

0

five

0

five

Signal 1 appears at the output of element 17. If there are more eggs, (in absolute value), then signal 1 remains at null 7. As a result, generator 5 is started and the pulse through open element 4 enters selector 3 and the scale switches scaling in block. If after that it turns out that / Ux / I isdd, /, then the signal O appears at the output of element 17. Element 4 is closed, element 10 is open and ADC clock pulses (Fig. 23) go to conversion in ADC 6. The results of scaling and conversions are derived from the device over tires 15 and 16.

The impulse voltage conversion mode is discussed in FIG. 1 and in the diagram of FIG. 3. To provide this mode, a signal 1 is applied to the input 28, which switches the device in the selector 24 and the block 21 to the mode of pulse voltage conversion. In this case, in the selector 24, in addition to the pulses coming from the generator 11, a Start impulse is formed (FIG. 3B) and a Start impulse (FIG. 3p) | preparatory unit 21 to work.

Block 21 operates in such a way that with the arrival of measured pulses it forms on the front of the second pulse after the Start signal (Fig. 31) a Sample signal (Fig. 3c). Potential Sampling transfers block 21 from tracking the signal Uy (Sampling mode) to the Storing (fixing) mode of the analog signal.

Thus, the measured pulse voltage 11., received on the input bus 13 of the device, passed through block 1 (FIG. 3) multiplexer 22, repeater 23, is fed to the input of block 21 and through multiplexer 22 to the input of null organ 7 ADC (FIG .3l). After the arrival of the trigger signal on the input bus 14, a single vibrator 12 is actuated (Fig. 3) and sets the device to its initial state. In the selector 24, a pulse starts to start, which appears at the output of the selector 24 after the initial installation of all elements of the device is completed. From the impulse A start on the front of the second impulse (Fig. 3p) triggers block 21 and outputs a Sampling difference (Fig. 3c). Block 21 goes into mode

0

five

0

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storage and switches the multiplexer 22 so that the signal from the output of block 21 is fed to the input of the zero-body 7 (Fig.3l). In addition, the same signal is fed to the input of the repeater 23, after which it is again fed to the input of block 21, which increases the storage time of the selected signal and increases the accuracy of storage. By the Sample differential (Fig. 3c), a start pulse is formed in the selector 24 (Fig. 36), by which the ADC Setting signal ends in the selector 25 (Fig. 3 d). In this case, the code O, 11, .. 1 is set at the inputs of the DAC 8, corresponding to a voltage of 0 (Fig. 3m). Further, by decay of the second ADC sync pulse (Fig. 33, a code is set at the inputs of the DAC that provides a voltage at its output or, if Uy Tszap, then code 1, 11 ... 1 (+ EOP) is generated, and if U; U then 0, 00 ... O (-EO „).

Thus, at the end of the positive differential of the second ADC sync pulse (Fig. 39), the signal O is set at the output of the element 18, and the signal 1 is output at the 1 9 element (Fig. W). .ZU), which starts the scaling mode. Differential Sampling (Fig. 3c), except the Start pulse (Fig. 3b) in the selector 2A, starts the Start-up pulse shaping mode, which goes to the output P of the selector 24 (Fig. 3) after completing all the switching and normalization in block 7. If If the output of block 21 (Fig. 3l) is less than U. q Qn of the primary value, then at the outputs of elements 18 and 19, the signals are reversed. After the arrival of the Start pulse (Fig.Zp) along the front of the second measured pulse (Fig.Zp), block 21 again goes from the Sample mode to the Storage mode, Block 21 outputs a control voltage drop (Fig. 1) to the first output (Fig. 1). CS), At the same time, a constant voltage appears at the second output for supplying it through the multiplexer 22 (FIG. 3L) to zero organ 7. As a result, the Start pulse (Fig. 3 &) is formed by the Sample differential (Fig. 3 &) D-flip-flop 27, inverted potential

0

15

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the output of which (FIG. 3) (c) opens element 10, and the sync pulses from the generator 11 enter the selector 25, and from there to the input of block 9 (Fig. 1.32) as sync pulses Poll of the zero-organ, as well as shifted to the time duration of one clock pulse (due to the time of voltage establishment in the DAC 8) clock pulses (Fig.ZZ), fed to the input of the A / D converter 6 for converting the constant voltage to the A / D converter as described. The output code for buses 15 and 16 is issued from the device.

Claims (5)

Invention Formula 1, An apparatus for measuring analog quantities with automatic scaling, comprising a one-oscillator, an analog-to-digital converter, performed in series connected to the control unit, digital-analog converter, null-organ, serially connected first clock generator, first AND element, pulse distributor, scale selector, zoom unit, serially connected second clock generator and second AND element, the second input of the zoom unit the first input bus one-shot input - second input bus scale selector outputs are the first output buses, the outputs of the control unit are the second output buses, series-connected elements EXCLUSIVE PTI, NAND and the first element NOT, the first input of the EXCLUSIVE OR element is combined with the first input of the control unit and connected to the output of the zero-body, the second input is combined with the input of the higher bit of the digital-to-analog converter, the output of the one-oscillator is connected to the first input of the first clock generator, the input of the second the sync pulse generator, the second inputs of the scale selector and the control unit, the output of the first element is NOT connected to the second input of the first element AND, characterized in that, in order to expand the field of application by providing the possibility of measuring pulse voltages, a sampling and storage unit is introduced into it, multiplexer. voltage follower, mode selector, sync pulse selector, second NOT element, D-flip-flop, sequential approximation register, whose outputs are connected to the corresponding third inputs of the control unit, the fourth and fifth inputs of which are connected to the first and second outputs of the sync pulse selector, the third and the fourth outputs of which are connected respectively to the first and second inputs of the sequential approximation register, the third input of the KOTopoio is connected to the second output of the control unit, the first inputs of the villages The mode and sampling and storage units are combined and are the third input bus, the second input of the sampling and storage unit is combined with the first input of the multiplexer and connected to the output of the voltage follower, the input of which is connected to the first output of the multiplexer, the second input of which is connected to the output of the changing unit the third input of the sampling and storage unit is combined with the second inputs of the pulse distributor mode selector, the first input of the sync pulse selector, the R input of the D flip-flop and is connected to the output of a single-oscillator The vertical input of the sampling and storage unit is connected to the first output of the mode selector, the third input of which is combined with the third input of the multiplexer and connected to the first output of the sampling and storage unit, the fourth and fifth inputs of the multiplexer are combined and connected to the second output of the sampling and storage unit, the second output the multiplexer is connected to the second input of the zero-body, and the second input of the selector clock is connected to the output of the second element And, the fourth input of the mode selector is combined with the third input of the selector clock , the second input of the second element And is connected to the non-inverting output of the D-flip-flop, the fourth input of the clock selector is combined with the input of the second element NOT and is connected to the second output of the mode selector, the output of the second element is NOT connected to the second input of the first clock generator and C-input D- trigger, D- the input of which is connected to the output of the NAND element, the second input of which is connected to the inverting output of the D-trig 0 five 0 gera, and the output of the second clock generator is connected to the fifth input of the mode selector. 2, The device according to claim 1, characterized in that the sampling and storage unit is made on a peak detector, a dual comparator, three NOT elements, two D-triggers, And element and the source of threshold voltages, the first and second outputs of which are connected respectively to the first the inverting and the first non-inverting inputs of the dual comparator, the second inverting and the second non-inverting inputs of which are combined and are the second input of the sampling and storage unit, the gating input of the dual comparator is connected to the inverting output the first D-flip-flop and the first output of the peak detector, which is the first output of the sampling and storage unit, the second output of which is the second output of the peak detector, the output of the double comparator is connected to the first input of the AND element and the input of the first element HE, the output of which is connected to C - the input of the second flip-flop, the D-input of which is combined with the D-input of the first D-flip-flop and is the first input of the sampling and storage unit; the R-inputs of the first and second D-flip-flops are combined and connected to the output of the second element HE, the input of which is The fourth input of the sampling and storage unit, the third input of which is the input of the third element NOT, the output of which is connected to the first C input of the first D-flip-flop, the second C input of which is connected to the output of the AND element, the second input of which is connected to the non-inverted 1M output of the second D-flip-flop. 3. The device according to Claim 1, which is based on the fact that the mode selector is made on a single vibrator, a frequency divider of the NOT element, a pulse counter, a multiplexer, two OR elements and a D flip-flop, the R input of which is connected to the output of the first element IL, C-input - with the first and second outputs of the multiplexer, D- input combined with the first control input of the multiplexer, which is the first input of the mode selector, S-input of the D-flip-flop combined with the first control input of the pulse counter and is the fourth mode selector input, D6 flip-flop output 0 five 0 five It is connected to the second control input of the pulse counter, the counting input of which is combined with the input of the element NOT and connected to the output of the frequency divider whose input is the fifth input of the mode selector; the first, second, third and fourth information inputs of the pulse counter are combined and are common bus, the input of the pulse counter installation is combined with the first input of the OR element and is the second input of the mode selector, the second input of the first OR element is connected to the first input of the second OR element and connected to the output of the single a torus whose input is the third input of the mode selector, the second input of the second I.PI element is connected to the third output of the multiplexer, and the output of the second OR element is the second output of the mode selector, the fourth output of the multiplexer is the first output of the selector mode, the first and the second information inputs of the multiplexer are combined AND connected to the output of the element NOT. 4. The device according to claim 1, about aphrases with the fact that the selector clock pulses are made on five elements EXCLUSIVE OR, the delay element, the element NOT, RS-trigger and two D-triggers, R-inputs RS- trigger and the first D-flip-flop and the first inputs of the first and second elements of the HCKJM) 4A- ORIGINAL OR are combined and are the first input of the clock selector S-input of the RS-flip-flop combined with the input of the delay element, the first input of the third element is BASTING OR, and is the fourth input the selector clock pulses, the output of the RS flip-flop is connected to the first input the third member EXCLUSIVE OR is the third output of the mode selector, the second input of the fourth element EXCLUSIVE OR is connected to the output of the first D-flip-flop, and the output to the first input of the fifth element EXCLUSIVE ISH1, the second input of which is connected to the output of the first element EXCLUSIVE OR, and output is P679210 the fourth clock selector input of the sync pulses, the second output of which is the output of the third IC-SPARING OR element, the second input of which is combined with the input of the element and is the second input of the sync pulse selector; D-inputs of the first and the second D-flip-flops are combined and, are the bus of the source of positive polarity, the C-inputs of the first and second D-flip-flops are combined and 15 is connected to the output of the delay element, the R-input of the second D-flip-flop is connected to the output of the second element EXCLUSIVE OR, the second input of which is the third input of the selector 20 sync pulses, the first output of which is the inverse output of the second D-flip-flop. 5. The device according to p., About tl and - the fact that the control unit 25 is executed on the D-flip-flop, two elements OR-NOT, n elements EXCLUSIVE OR, where n is the number of bits of the analog-digital converter, , the first inputs of which are respectively the third inputs of the control unit, the second input of the nth element EXCLUSIVE OR is the common bus, the second input of the (n − 1) -th element EXCLUSIVE OR is connected to the output of the first Element OR NOT, the second inputs of the elements of the TEXT. STUDY OR from the first to (n-2) -th are combined and connected to the output of the second element OR-FiE, the outputs of the elements EXCLUSIVE OR are Q, respectively, the first outputs of the control unit, the second output of which is the inverted output of the D-trigger, which is connected to the first input of the second element PTI-NOT, vto., - a swarm whose input is combined with the first input of the first I1B1-NOT element and is the fourth input of the control unit, the second input of the first OR-NOT element is connected to the direct input of the D-grigger, S-, D- and The C inputs of which are respectively the second, first and fifth control unit inputs. 50 cpuaZ sriR.Z R D / 2 h s BUT . 21 L fV H- V2 with; five