SU1290529A1 - Delta coder - Google Patents

Abstract

The invention relates to automation and communication technology. Its use in transmission systems makes it possible to increase the functional reliability and reliability of the conversion. The delta coder contains a comparator, a trigger, a shift register, four AND elements, an OR element, a NOT element, two counters, a decoder, two buffer registers, an equivalence element, a constant memory block, a reversible counter, a multiplexer block, a digital-analog converter and arithmetic logic unit. In addition, an additional counter, an OR element, two decoders, and two elements: does NOT provide for blocking a reverse counter in extreme states, as well as the possibility of additional synchronization of the transmitted signal. 1 il. a (L to so about a y QD

Description

The invention relates to automation and communication technology and can be used in signal transmission systems (e.g. voice).

The purpose of the invention is to increase the functional reliability and reliability of the conversion.

The drawing shows a functional diagram of the device.

Delta coder contains comparator 1, trigger 2, shift register 3, first 4, second 5, third 6 and fourth 7 elements AND, first 8 and second 9 elements OR, first 10, second 11 and third 12 counters, first 13, second 14, third 15 and fourth. 16 decoders, first 17 and second 18 buffer registers, first 19, second 20 and third 21 elements .NE, equivalence element 22, fixed memory block 23, reversible counter 24, multiplexer block 25, digital-to-analog converter (DAC 26, arithmetic logic unit 27, information) 1st input 28, input 29 synchronization and output 30.

The device works as follows.

The analog signal arriving at the device information input 28 is compared in comparator 1 with the approximating signal from the DAC 26. The resulting digital sequence is sampled in the trigger 2 by the synchronization signal from input 29 and fed to device 30, as well as in shift register 3 the outputs of register 3 are analyzed by elements 4 and 5, RSHI 8, the first counter 10 and the first decoder 13. At the same time, the second counter 1-1 counts the clock pulses from input 29. The result of the calculation is compared on the equivalence element 22 the number of blocks 23 fixed memory locations corresponding to a predetermined interval T. analysis. At the expiration of each interval, T. counters 10 and 11 are zeroed. If at the same time for time m T. in the output signal of the delta coder, the number of double characters (ones or zeros) did not exceed a certain number N, | flj;, H, then there are no signals at the outputs of the first decoder 13, if this number is greater than a certain number M „„ „“, then the signals are present

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torus 13. When the number of double characters is between N and N. The signal is only on the first output; decoder 13. At intervals Td, signals from decoder 13 are written to the first buffer register 17, and the signal from its first output is inverted by the NOT element 19. At the end of each interval T, elements 6 and 7 are opened and pass the corresponding signals to the inputs of the reversible counter 24. As a result, if the double characters are smaller, the content of the reversible counter 24 is reduced by one, and if the double characters are greater than N., the content is increased. The signals from the reversible counter 24 by means of the multiplexer block 25 control the connection to the arithmetic logic unit 27 from the block 23 of the permanent memory of signals corresponding to the required (larger or smaller) quantization step. The arithmetic logic unit 27, in combination with the second buffer register 18 and the D / A converter 26, represents the approximate voltage recovery unit.

The third counter 12 counts clock pulses from input 29, while the presence of double pulses in the output signal of the delta coder causes the counter to be zeroed out 12. Thus, counter 12 counts the number of sync pulses in the pauses of the input signal and upon reaching a certain number chosen according to that there is practically no free channel noise in the idler signal of the delta coder, the second decoder 14 results in a signal that the second counter 11 flushes through the second element OR 9. decoder and decoder, the second counter of the encoder 11 and the analog decoder counter work synchronously at the end of the pause, thereby increasing the reliability and reliability of the conversion.

The third and fourth decoders 15 and 16 fix the state of the reversible counter 24 corresponding to the minimum and maximum quantization steps. The signals from these decoders after inversion on the elements HE 20 and 21 prohibit the passage of signals through the elements 6 and

7 to the corresponding inputs of the reversing counter 24. As a result, the encoder is prevented from idle running from the minimum and maximum quantization steps in the idle mode, and from the maximum to the minimum in the overload mode because of the overload, and also increases the reliability of the conversion and the reliability of the device.

Claims (1)

Invention Formula A delta coder containing a comparator, the first input of which is the information input of the trigger device, the shift register, the first and second counters, the first decoder, the permanent memory unit, the arithmetic logic unit, the reversible counter, the multiplexer unit, the first and the second buffer registers, the equivalence element, the first element is NOT, the first element is OR, the first, second, third and fourth elements are AND, and a digital-analogue converter, the output of which is connected to the second input of the comparator, the output of which is connected to the trigger input, the output of which, being the output of the device, is connected to the control input of the arithmetic logic unit and the information input of the shift register, the forward and inverse outputs of the first and second bits of which are connected to the first and second inputs, respectively and the second elements D, the third inputs of which are combined with the synchronization inputs of the shift register and the trigger, the counting input of the second counter and the zero input of the second buffer register and connected to the device sync input, outputs ervogo and second AND soedi- nen to the inputs of the first OR gate whose output is connected to the counting input of the first k counter, which outputs are connected to respective inputs of the first decoder, the first and second outputs which are connected to sootvetstvuyuschim- informatsionnm the inputs of the first buffer register, the first output of which is through the first element is NOT, and the second is directly connected to the first inputs of the third and fourth elements, respectively, the second inputs of which are combined with the zeroing inputs of the first counter and the buffer register and connected to the outputs of the equivalence element, the first and second inputs which are connected respectively to the inputs of the second counter and the first outputs of the block of permanent memory, the second outputs of which are connected to the information inputs of the block of multiplexers, the equal inputs of which are connected to the outputs of the reversible counter, whose forward and reverse counting inputs are connected to the outputs of the fourth and third And elements, respectively, the outputs of the arithmetic logic unit are connected to the information inputs of the second buffer register, the outputs of which are connected to the corresponding inputs of the digital-analogue converter and the first inputs of arithmetic logic . block.a, characterized in that, in order to increase the functional reliability and reliability of the transformation, the second, third and fourth decoders, the second OR element, the second and third NOT elements and the third counter, whose counting input is combined with the second counter, are entered into it counter, zeroing input is connected to the output of the first element OR, and the outputs are connected to the corresponding inputs of the second decoder, the output of which is connected to the first input of the second element OR, the second input of which is connected to the output of the equivalent element The output is connected to the zeroing input of the second counter, the outputs of the multiplexer unit are connected to the corresponding second inputs of the arithmetic logic unit and the inputs of the third and fourth decoders, the outputs of which are respectively connected to the third and fourth elements of the third and fourth elements respectively Compiled by 0 „Revinsky Editor L, Pcholkna Tekhred I. Popovich Corrector A.T. 7916/57 Circulation 9 2 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 11 production 7 printing company, Uzhgorod, st. Project, 4