SU1280642A2 - Device for exchanging data between group of input-output channels and internal memory - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the development of processors whose equipment is used in the transmission of data between input / output channels and main memory or input / output systems. The aim of the invention is expansion. functional capabilities of the device due to the organization of a common field of subchannels for the purpose of flexible adaptation to user conditions, both in terms of efficient use of memory volumes intended for storing subchannels and in the possibility of connecting a certain number of peripheral devices to each I / O channel from groups

Description

"

but

Cg-enals. The device contains firmware control block 1, input register 2, register 1, register A, switch 14, control block 17, 6JTOK IP, request priority, group of matching blocks 19, job register 23, switching node 24, block 25

priority encoders, block 26 registers, node 27 decoders, two groups of 15, 16 registers, two groups of 5, 2P elements of ISH, two triggers 7, 11, element OR 12, two elements AND 6, 13, two elements of IS AND 8, 1P. 10 il.

one

The invention relates to computational techniques, and can be used in the development of processors whose hardware is used in transferring data between I / O channels and main memory or in I / O systems.

The purpose of the invention is to expand the functionality of the device by organizing a common field of subchannels to provide flexible adaptation to user conditions, both in terms of efficient use of storage space intended for storing subchannels, and in terms of connecting one or more JHHoro peripheral devices to each input channel. - output from a group of channels.

The job register contains an n-bit register and a group of n switches, where the output of the n-bit register is connected to the information output of the node, the first contact of each switch from the group is connected to the input of the corresponding bit of the n-bit register, and the second contacts are n The switches are connected to ground.

Introduction to the device register for. Daniyan gives the chance individually for each user to choose and establish necessary and optimum; the amount of memory for storing subchannels.

Fig. 1 shows a block diagram of a device for exchanging data between a group of I / O channels and random access memory; Fig. 2 is a functional block diagram of a firmware control unit; FIG. 3 is a functional block diagram of the control unit; Fig. 4 is a functional diagram of an agreement block; Fig, 5 is a functional block diagram of priority encoders; figure 6 is a functional block diagram of registers; Fig "7 is a functional diagram of the node decoder; Fig. 8 is a time diagram of the execution of the microcommand MEMORY when the processor accesses it; Fig. 9 is a timing diagram of the execution of a microcommand. Memory read from RAM to channels; Fig. 10 is a timing diagram of the execution of a microcommand. Write memory to the RAM from channels.

A device for exchanging data between a group of I / O channels and random-access memory contains a block 1 of firmware control, input register 2, random access memory 3, output register 4, the AND-OR 5 element of the first group, the first And 6 element, the first trigger 7, the first element IS-NE 8, the third trigger 9, the second element IS-NOT 10, the second trigger 11, the element OR 12, the second element AND 13, the switch 14, registers 15 and 16 of the first and second groups, respectively, control block 17, block 18 priority of requests, a group of blocks 19 approval, the element AND-OR 20 of the second group, with the input device 21, groups of information I / O 22, job register 23, switching node 24, priority encoder block 23, register block 26, and decoder node 27.

The microprogram control unit 1 consists of memory of 28 micro-instructions, address register 29, register of micro-instructions 30, decoder 31, local memory 32, second 33 and first 34 registers, logical arithmetic unit 33, result register 36, first 37 and second groups 38 elements AND-OR, element 39 and element-NONE Block 1 has the first 41 and second 42 and formation inputs, mode input 43, gate input 44, permission input 45, gate rotor 46, gate output 47, address output 48, first to fifth control outputs 49-53, sample output 54, third information The input 55 and the group of control outputs 56 decryption unit. The control block 17 contains a data transfer trigger 57, a group of data transmission trigger 58 and 59, AND elements 60 and 61 of the first group, second 62 and first 63 OR elements, first 64 and second 65 AND elements, HE element 66, data transfer request trigger 67 , trigger 68 of the first transmission cycle, trigger 69 of the intermediate transmission cycle, trigger 70 of the second transmission cycle, group of triggers 71 and 72 of the second transmission cycle of channels, elements 73 and 74 of the second group, group of elements AND-OR 75 and 76, first 77 and second 78 elements AND-OR, elements AND-OR 79 and 80 of the first group and ale nty and-or 81 and 82 of the second group. Unit 17 has the first to fourth groups of inputs 83-86, the first 87 and the second 88 inputs, the first to the fifth outputs 89-93, and the first to the third groups of outputs 94-96 of the block, respectively. The matching unit 19 constitutes data register 97, data buffer memory 98, interface reversal trigger 99, interface buffer selection trigger 100, byte address counter 101, processor buffer selection trigger 102, word number trigger 103, double word counter 104, first 105 and second 106

synchronization wells, switch 107, interface exchange 108, data register trigger trigger 109, register group trigger 110, opcode register 111, de-. encoder 112, elements AND-OR 113 and 114 of the first and second groups, first to sixth elements AND-OR 115-120 and element AND-OR-NOT 121, Block 19 have the first 122 and second 123 information inputs, information input-output 124, resolution input 125, synchronization input 126, information output 127, first 128 and second 129 synchronization outputs, request output 130, write output 131 and read output 132.

Block 25 priority encoders contains (in this case) four

the progress of the decoder 112 determines that a read operation is performed in the matching unit.

When reading data, the data from the peripheral device is byte-byte from the information input-output of block 19 via the switch 107 to the data register 97, from which, through the first group of AND-OR 113 elements, the data is written to the buffer memory 98 at the output of the second group of elements AND- OR 114,

If the trigger 110 for the group of registers is reset, after accumulating a double word in the buffer memory, first reading the first word from the buffer memory and transmitting it through the information to the input priority 133-136 encoder, one four-input priority encoder 137 and three multiplexers 138-140 as well as information input 141 multiplexers, information outputs 142 and 143 of the encoder 137 and its information input 144 and output 145. Block 26 of the registers consists of two one-bit registers 146 and 147, two two-bit registers 148 and 149, two three-bit registers 150 and 151, its Information input 152, group entry 153 and the first 154 and second 155 information outputs, as well as outputs 156 and 157 registers 150 and 151, Node 27 decoders contains two decoders 158 and 159 , information input 160 and information output 161, the Device operates as follows. Buffer memory 98 has two data zones. The capacity of each of the zones corresponds to the size of the RAM and in this case is a double word (eight bytes). The width of the buffer memory corresponds to the width of the information path of the processor (in this case it is one word), through the paths of which the channel exchanges data with the main memory. The Operation Code, executed by matching unit 19, is located in the operation code register 111. The second output signal of the decoder 112 determines that in block 19 one of the recordings is performed. The signal from the first high output of block 19, the second group of AND-OR elements 20 and the first group of registers 15 to the second group of registers 16, then reading the second word and transferring it to the first group of registers 15. After filling the registers, the trigger 110 of the group of registers set to one. For the read operation in this case, the third element AND-OR 117 generates a request for data transfer, which through the output of the request of block 19 enters the input of the block 18 of the priority of requests. During the recording operation, during the second cycle of data transmission of the corresponding channel, a trigger for triggering 110 of the register group is detected by a signal received at the resolution input of block 19, registering the availability of data received from the primary memory in the first and second groups of registers 15 and 16 corresponding channel. If in the data buffer buffer 98 one of the zones is free, the first word of data from the second group of registers 16, and then the second data word is transmitted first through the second information input of block 19 and the first group of D-OR elements 113 to the buffer memory 98, Data from the buffer memory 98, via the second information input of the switch 107, are received into the data register 97, from where they are output to the information input / output of the block 19 under the control of the exchange node 108 via the interface and the data register trigger 109. During a write operation, the request for data transfer is established using the third AND-OR element 117, if the trigger 110 for the group of registers is cleared. The read operation signal from the first output of the decoder 112 and the write operation signal from the second output of the decoder 112 are respectively supplied through the read outputs 132 and the write 131 of block 19 to the group of AND-OR elements 20 and to control the loading direction of the first and second groups of registers 15 and 16 to the block 17 controls An interface call trigger 99 is used to control the data buffer addressing. If the interface call trigger 99 is reset, then when exchanging data between the buffer data memory and the register group, the buffer memory is up to / 42 of the double word zone using the processor buser trigger 102, and with the word number trigger 103 . The word number trigger 103 is switched during the transmission of a double word. If the interface call trigger 99 is set, then the exchange between the buffer memory and the register 97 can be performed. In this case, the zone is addressed using the interface buffer trigger 100, and the word and byte inside the word are addressed using a three-byte counter 101 byte address, Lvukhrazr A single double word counter 104 indicates the number of double words in the data buffer 98. During the write operation, it shows the number of empty double words in the buffer memory 98, during the read operation the number of filled double words. At the beginning of the write operation, the counter is set to 2 (two double words not filled), Q) jj go the time of transfer of the double word from the groups of registers 15 and 16, its contents are reduced. After a double word is transmitted via the interface, the contents of the double word counter 104 are increased. At the beginning of the read operation, the counter is set to O and is modified accordingly during data exchange. The control of the operation of the equipment of block 19 during data transfer between the buffer memory 98 and the register 97 is performed by the node 106. The control of the data transfer between the buffer memory 98 and the group of registers 15 and 16 is performed by the node 105. This node generates the load gates first and the second groups of registers 15 and 16 of the corresponding channel, which are received, respectively, when transferring data to the buffer memory or from the buffer memory to the first and second synchronization inputs of block 19, the node 106 is started via an ANDI element NO-121, and the launch of node 105 through the fifth AND-OR element 119, Requests from all blocks 19 are received at block 18, which receives them via a synchronizing signal, determines the most priority of them, and transmits to block 17, in which a data transfer trigger 57 is set up and one of the trigger group 58

and 59 data channels that indicate which unit 19 should exchange data. The input of block 17, to the second group of inputs, from block 19 receives the operation code, which is used for instrumental generation of the access microcommand and RAM in the first group of elements AND 60 and 61 and the second element OR 62, from the output of which the microcommand enters the mode input block 1 into the micro-command register 30 through the first group of elements AND-OR 37, and the potential from the data transfer trigger 57 of block 17 blocks the reception of micro-instructions from memory 28 of the micro-commands of block 1 to the first group of elements AND-OR 37 and passes the micro-command and From block 17, during the execution of which the data must be exchanged between the RAM and the first and second groups of registers 15 and 16 through the internal paths of the processor.

To control the data flow, unit 17 generates a sequence of signals from the outputs of the trigger 67 for sending data, trigger 68 for the first transmission cycle, trigger 69 for the intermediate cycle for triggering 70 for the second transmission cycle, for controlling the first and second groups of registers 15 and 16 for the outputs of the first and second groups of elements AND-OR 79-82.

The microcommand Memory runs in two cycles,

In the first cycle, the data address is prepared. Data is recorded when the memory is written to it. Reading and writing is done in the pause between the first and second cycles. The length of the pause depends on the time it takes to access the memory. This time is much longer than the first and second memory cycles. In the second cycle, in the case of reading, data is selected from the memory and sent through internal paths. The processor is in the first and second group of registers 15 and 16, the data request request trigger 67 of block 17 uses two runs of hardware-generated microcommand Memory, Block 18 is designed to select top priority channels.

The switch 14 serves to select data from the main memory or result register 36 of block 1 and is a group of AND-OR elements.

Fig. B shows a time diagram of the operation of the device for exchanging data between a group of I / O channels and random access memory for executing micro-instructions Memory when the processor accesses it. The following symbols are used in the diagram: a - synchronization; S — reception in the first register 34 of a memory address; 6 - reception of the double data word in the output register 4; 2 — an entry in the local memory 32 of the modified memory address; a - the first word of data from the first group of elements AND-OR 5; e - the output of the third trigger 9; zhvacha second data word from the first group of elements AND-OR 5; control switch 14 to select data from the RAM; U record the first data word; k - write the second data word.

The device for executing the microcommand Memory, when the processor accesses it, works as follows.

From the memory 28 of the micro-instructions of block 1, the address from the register 29 of the address, through the first group of AND-OR elements 37 and the register 30 is entered into the micro-command that goes to the decoder 31, from the seventh output of which the local memory 32 is fed to the first The register 34 reads the address of the RAM data, which, through address-output 38 of block 1, is fed to the address output of the device in RAM. The double data word and RAM is entered into the output register 4, from which, using the first group of AND-OR 5 elements, the first data word is fed to the switch 14. The selection of the new word is controlled by the first AND-NE 8 element of the installed first trigger 7, which is established through the first AND 6 element by the low byte of the double word address from the first register 34 of block 1. The RAM data address is also fed to the arithmetic logic node 35 in which it is modified and through the result register 36 and the switch 14 is recorded in the local memory 32. After that, the control of the switch 14 on the output of the second element I 13 switches to the selection of the first data word from the operational memory After recording the first data word, the second output of the decoder 31 of block 1 is set to trigger 9, which inverse output to the first element I.6 changes the lower address of the RAM, which is stored at the end of the microcommand. Memory on the first trigger 7 and through the first element AND-NE 8 changes the control of the first group of AND-OR elements 5 and for issuing the second Data word from the output register 4 to the switch 14, and the direct output of the third trigger 9 controls the transmission of this data word through the switch 14 against the background eduyuschey microcode.

Fig. 9 shows a time diagram of the operation of the device for performing hardware-formed microcommand Memory read from a RAM. The following symbols are used on it: a - synchronization; S is the trigger output 68 of the first transmission cycle; L is the output of the 69 intermediate transfer cycle trigger; 2 - the output of the trigger 70 of the second transmission cycle; a — reception in the first register 34 of the memory address and byte counter; 6 - reception of the double data word in the output register 4; K - the first word of data from the first group of elements AND-OR 5; issuing a second data word from the first group of I-IPI 5 elements; U - the output of the second trigger 11; control switch 14 to select data from main memory; -l - an entry in the local memory 32 of the modified memory address and byte counter; m strobe of the first group of registers 15; H - the strobe of the second group of registers 16; The device, when reading data from the RAM into the first and second groups of registers 15 and 16, works as follows: From block 17 to block 1 to register 30, a hardware-generated micro-command is entered, which goes to decipher 31, from the seventh exit to the local memory 32 is fed

the address to which the first register 34 in the first memory cycle counts the address of the RAM data, which is fed to the address output of the device to the RAM and to the arithmetic logic unit 35 on which it is modified. The double data word is read from the RAM into the output register 4. The low byte of the RAM address that addresses the first data word from the first register 34 of block 1 through the first element AND 6 sets the first trigger 7, which through the first element AND-NOT 8 controls E by selecting the first data word on the first group of elements AND-OR 5, which goes to the switch 14, From the output of the data transfer trigger 55 of the block 17, the information input of the second trigger 11 is given a signal that sets this trigger at the beginning of the first

cycle of microcommand Memory, Second trigger 11 controls the transfer through the switch 14 of the first word of data from the operational memory that passes through the second group of elements

AND-OR 20 under the control of the write output of block 19 and through the first group of registers 15, since a constant gate is applied to the synchronization input, is latched into the second group of registers 16 along the gate formed on the first group of elements AND-OR 79 and 80 of block 17 the signals from the output of the group of triggers 58 and 59 of data transmission channels and the trigger 70 of the second

which, through the switch 14 under the control of the signal from the output of the second element, And 13 enters through the second transmission cycle and the synchronization signal. From the local memory 32 of block 1 in the second cycle of memory to the first register 34, the byte count is read, which remains to be transferred from the main memory to the channels. The byte counter is transmitted to the arithmetic logic unit 35 on which it is modified. After resetting the second trigger 11, the control of the switch 14 switches to issuing from the register the result 36 of the modified address, which is recorded in the local memory 32, then at the second AND-NE 10 element according to the output signal of the trigger 70 of the second transmission cycle of the unit 17 and the signal from the device's synchronous input 21, a signal is generated which is supplied to the second input of the first element NAND 8 and inverts the outputs of this element. Thus, the first group of elements AND-OR 5 selects the second word dan group of elements I-IL 20 onto the first group of registers 15 and latches along the gate formed on the second group of elements I-STI 81 on signal 1 from the output of the group of triggers 58 and 59 ne11:

data transmission channels, the sync signal from the output of the group of triggers 75 and 76 of the second cycle of transmission channels. A modified counter is recorded from the register 36 of the result of block 1 into the local memory 32 against the background of the following microinstruction,

FIG. 10 shows a diagram of the operation of the device for performing hardware-generated microcommand Memory in RAM. The following notation is used in the diagram: a - synchronization; & trigger output 68 of the first transmission cycle; B - output of the intermediate transfer cycle trigger 69 ;; 2 - reception of the memory address in the first register 34; J - receiving in the second register 33 data from the second group of registers 16; e - receive data in the input register 2; W - gate of the second group of registers 16; 0 - write to the RAM.

A device for recording data from the first and second groups of registers 15 and 16 into the RAM operates as follows.

From the second information output of the group of registers 16 to block 1 to the second register 33, through the second group of elements AND-OR 38, under the control of the signal from the output of the data transfer trigger 57 of block 17, the first gate data word is received from the output of the first element AND-OR 77 of block 17, which is generated on a clock signal. After receiving the first word in the second register 33 of block 1, the data through the first control output 51 of block 1 is fed to the input register 2, in which it is received via a gate formed on the second element AND-OR 78 of block 17, which is generated by the sync signal and the third to the control output of block 1, after receiving the first data word in input-register 2, the second data word from the first group of registers 15 is rewritten into the second group of registers 16 by the gate from the output of the first group of elements I-IZH 79 and 80 of block 17, formed from signals out Yes, groups of trigger 58 and 59 of transmission, data of channels, trigger 68 of the first transmission cycle and clock signal. From the output of the second group of registers 16, the second data word is written into the second register 33 of block 1 via the second group of AND-OR 38 elements through the gate

8064212

from the output of the first; element AND-OR 77 of the block 17, generated by the signals from the output of the data transfer trigger 57, the trigger 68 of the first cycle

from the transmission and the clock signal; From the output of the second register 33 of block 1, the second data word is fed to the input register 2, on which it latches on the gate from the output of the second evil AND-OR 78 of block 17, generated from the signals from the output of the data transfer trigger 55 and sync signal. From the local memory 32 of block 1, the address is read, which through the first f5 register 34 is transmitted to the address output of the device in the operational memory. On the fifth output of the decoder 31 of block 1 on the element I 39, a gate of replacements is produced in the RAM, which is fed to the gate output of the device.

The organization of a common subchannel field in the device for data exchange between a group of I / O channels and 25 RAM is performed by hardware-firmware method.

The device in this case works as follows

30 The hardware part of the implementation of the common subchannel floor is based on the use of the register of 23 tasks, switching node 24, block 25 priority encoders, block 26 registers, 2 nodes 27 decryption. The firmware part of the implementation of the generalized field of subchannels is based on the use of the processor’s hardware, which includes a device for

40 data exchange between a group of I / O channels of RAM, wherein the processor controls the operation of a group of I / O channels using special I / O commands,

45 A channel program is accessed using the channel address word located in a fixed memory cell. The channel address word contains the security key and

50 is the address of the first control word of the channel, which is initially located in the RAM.

A channel program consists of a sequence of control words of a channel. Channel control words contain all the necessary information for organizing and conducting communication of an I / O channel with a peripheral device. In order to ensure that the control word of the channel control word from the memory memory is efficient from the point of view of performance of the channel control word, it is copied into certain cells ( subchannels) of faster local memory in which the channel control words are kept until the end of the I / O channel operation with the peripheral device.

When a single channel of input from a group of channels with several peripheral devices is operating simultaneously, as many channel control words as the peripheral devices are simultaneously running across the entire group of channels in the local memory. Thus, the possible number of simultaneously running peripherals is determined by the number of subchannels, i.e. by that maximum amount in the local memory which is allocated for storing the total number of control channels. Thus, in order to maximize the address field of peripheral devices for each channel, which determines the maximum possible Number of peripheral devices that can be connected to one I / O channel (and in this case 256 devices), you need to allocate enough space in the local memory storing 256xp subchannels (where n is the number of I / O channels in the group). If we consider that four thirty-two-word words need to be allocated in local memory for storing one subchannel, and the fact that not every user needs such a number of subchannels, the option of providing the maximum number of subchannels is not optimal.

The organization of a common field of subchannels with their dynamic assignment allows, first, to optimally redistribute subchannels between a group of channels, and secondly, with the optimal number of subchannels, it is possible to organize the possibility of connecting to each input / output channel the maximum number of peripheral devices.

The selection of the optimal number of subchannels is accomplished by switching in register 23 manually using

switches or otherwise appropriate bits (in this case, the thirty-two-bit register) so that the inLormation output register 23 of tasks received a 32-bit code defining the selected number of subchannels. When executing a firmware reset system that runs

every time when the command system is loaded or after pressing the System Reset button on the operator’s console, this code is read by the read microcommand decoded on the decoder 31 and read 5 by a read signal from the output group 56 from the register 23 through node 24, the third information input 55 of block 1, element I-IPI 38, register 33, arithmetic logic unit 35, register 36

0 result, the second control output 53 of unit 1, the first input of switch 14, the first information input 41 of unit 1 and is recorded as standard. Thus, in a certain cell of the memory 32 as a characteristic of the number of subchannels allocated in the local memory for a group of I / O channels. In the future, this information is used every time when the next I / O instruction is issued for assigning a free subchannel. If there are no free subchannels, the I / O command is terminated.

At the same time, the channel microprogram generates such an indication of the result, which would have been formed if during the execution of the input-output command it turned out that the required peripheral device does not exist. Such an algorithm for generating a result attribute in the absence of free subchannels is selected from the calculation to indicate to the user that with the existing number of peripheral devices connected to the I / O channel group, the selected number of subchannels is not enough. This conclusion should be made by the user when the operating system (or any other system) standardly reports that there is no specific peripheral device, but in fact it is connected and functioning normally. By changing the total number of subchannels in one direction or another, the user individually selects for his own needs the optimal number of subchannels. The organization of connecting the maximum number of peripheral devices to each I / O channel from the channel group is accomplished by randomly assigning subchannels, i.e. by the possibility of assigning any subchannel to any peripheral device with a further release of this subchannel after the end of communication with the peripheral device. The arbitrary assignment of pods in this case is performed in a hardware-firmware manner. This uses the hardware of node 24, blocks 25, 26, and (node 27. In addition, tables located in the local memory and several local memory cells are used for the operational processing of control information. The first table contains 256 consecutively addressed cells local memory, each of which is intended to store the address of the assigned subchannel for a specific peripheral device. The addressing cells of this table correspond to the addressing of the maximum number of peripheral devices that could They can be connected to one I / O channel. The number of first tables is determined by the number of I / O channels in a group. The first table is also used to store a sign that indicates whether a subchannel is assigned to a peripheral device or not.

the sign is established. After the end of the peripheral operation, when the subchannel is not needed, this flag is reset.

The second table containing In this case, the thirty-two 32-bit words, together with the word pointer of the second table, which in this case consists of one 32-bit word, is used to form the address of the free subchannel. The second table defines the maximum number of subchannels that can be assigned to a group of channels (in this case 1024). The actual number of assigned subchannels is determined by correcting this table and the pointer to the second table.

at least one free subchannel defined in one word of this table is characterized by the corresponding

The second table at address 3 is not. Considering the above, the initial installation of the corresponding number of subchannels, which is determined by the code read from register 23, is implemented microprogrammatically by setting the corresponding number of bits in the second table and in the index of words of this table in one state.

50 . During the execution of an I / O command, according to the channel number and the address of the peripheral device indicated in the I / O command being executed, the corresponding word is selected from

55 of the first table and is stored in one of the local memory cells. The purpose of this sample is to determine whether the addressable in the I / O command in accordance with C is free; the characteristic of the number of subchannels merged into the local memory for the I / O channel group indicated by the code counted from the 23 jobs register. The word pointer of the second table is used to quickly find a free subchannel from the total number of allocated subchannels. The formation of the address of a free subchannel is performed by determining the five-bit address of the second table (the upper bits of the sub-channel address) and the five-bit address of the bit in this word (the lower bits of the subchannel address). Since the address of the word of the second table is determined by the bit address in index of the second table, the address of the free subchannel is normalized from the bit address in the index of the second table and the bit address in the corresponding word of the second table. The formation of the free subchannel address for a specific peripheral device is performed as follows. The total number of subchannels is specified by setting the total number of bits in the words in the second table to zero. Moreover, the presence of 35 bits of the pointer of the second table, set to the zero state. For example, if bit 3 of the pointer of the second table is set to 1, then the free subchannels of addressed words

peripheral device or not, which is accomplished by analyzing the destination attribute, the subchannel.

If a subchannel is assigned, therefore, a peripheral device addressed to the I / O command is busy, the execution of the I / O command is terminated.

If no subchannel is assigned, the peripheral device is free, performed fO

The I / O command continues.

An attempt is made to assign a free subchannel. For this purpose, the availability of free sites is analyzed.

channels. The analysis is performed by determining the presence of zero bits in the pointer of the second table. If there are no zero bits, t, e, there are no free subchannels; the I / O operation is terminated. If there are free subchannels, the address of the free subchannel is formed as follows.

The pointer of the words of the second table from the local memory through the register 34, the arithmetic logic unit 35, the result register 36, the control output 53 and the switch 14 enters the block 25 of priority encoders. Through the information input 14 from the first to the fourth bytes of this word are fed to the inputs From first to fourth priority encoders 133-136 respectively. Thus, the addresses of the first zero bits of each byte of the spruce are formed at the address outputs of the priority encoders 133-136. In this case, if there are no zero bits in the byte, the corresponding priority encoder initiates its control output. Therefore, if there is no zero zero bit in the second word table pointer, the control output of the first priority encoder 137 is excited, which is connected via line 14 to information output 145 If there are free subchannels, then a two-bit address removed from the address output the priority encoder 137 indicates the address of the first byte of the pointer of the words of the second table, in which there is at least one zero bit, and the three-bit address taken from the outputs of the multiplexers 138140 indicates the address of the bit in the corresponding byte, Duplex the second byte address along the lines 142 and the three-bit address bit along the lines 141 are connected

with information output 145 of block 25; Thus, with the help of block 25, hardware analysis of the presence of free subchannels and the formation of the address of the second table, which has free subchannels, is performed,

 The information received at the information output 145 of block 25 on the micrator 31 by a write signal, removed from the group output of the decryption 156 of block 1, is written to the registers via the group input 153- of the record of block 26

and 141 and is remembered for further analysis.

Analyzing the information removed from the output of register 146 through the first information output 154 of block 26, the presence of free subchannels is determined. If there are free subchannels, from the outputs of registers 148 and 150 are a five-digit code, from which the second

Claims (1)

the corresponding 32-bit word is read into one of the local memory cells, which is then output to block 25, and according to a special micro-command, the information received by the rocomand decoded to decrypt 148 and 150 by lines 143, 142 is stored at information output 145 of block 25, block 26 on registers 147, 149, and 151. Thus, after analyzing two 32-bit word words, a second table, and one of the words of the second table, the first information output 154 of block 26 forms: with a ten-digit code, which is the address of the free subchannel . This address is read and then entered in the first table along with the tag. indicating that a subchannel has been assigned to a specific peripheral device. After the subchannel is assigned, the word of the second table is corrected and, if necessary, the pointer of the words of this table. For this purpose, the address codes of the bit in the pointer byte of the words of the second table and in the byte of the corresponding word of this table are sent via lines 156 and 157, respectively, through the second information output 155 of block 26 to node 27 to the inputs of the decoders 158 and 159. At the outputs of the decoders 158 and 159 the corresponding constants are set, which are used to adjust the corresponding byte of the word of the second table and, if necessary, the corresponding byte of the pointer of the words of this table. After adjusting the byte in the word of the second table, this word is checked for the presence of free subchannels in it. For this purpose, the corrected word of this table is fed to block 25 and the result of the analysis of the presence or absence of free subchannels is stored in register 147, analyzing the contents of this register, it is determined that the pointer of the second table should be corrected and, if necessary, the pointer of the table pointer of this table is corrected using a constant- read from the outputs of the decoder 158, the assignment of the subchannel for a specific peripheral device is completed. The release of the subchannel is performed after the end of the channel communication with the periarial device when the corresponding subchannel is no longer needed. The subchannel is mastered by a microprogram method, Formula of the invention A device for exchanging data between a group of I / O channels FIG. 2 and operative memory of aut., Cf., No. 1190385, characterized in that, in order to expand functionality by organizing a common field of subchannel memory, a job register, a switching node, a block of priority encoders, a block of registers, a decoder node, are entered into it, moreover, the information output of the register of tasks is connected with the first information output of the node com; numerical information, the second information input of which is connected to the first information output of the block of registers, the second information output of which is connected to information inputs. the decoder node whose output is connected to the third Information input of the switching node, the output of which is connected to the third input of the logic conditions of the microprogram control unit, the control output group of which is connected to the group of control inputs of the switching node and the information input of which is connected with the inputs of the block of priority encoders, whose information input is connected to the output of the switch. / 52 (Reg. 4 flf ".5 wo