SU1278867A2 - Device for exchanging data between group of input-output channels and internal memory - Google Patents

Abstract

The invention relates to computing and can be used in the development of processors whose equipment is used to transfer data between I / O channels and main memory. The aim of the invention is to increase the capacity of the device by organizing the possibility of assigning any priority to any I / O channel from the group at the time the I / O operation is performed, depending on which peripheral device the channel organizes the data transfer with. This makes it possible with maximum efficiency to use less priority channels due to the possibility of connecting to them the same peripheral devices that can be connected to the priority I / O channel itself. The device contains a firmware control unit, input and output registers, two groups of I-SHS, c & two AND elements, three triggers, two AND-NOT elements, an OR element, a switch (L tor, two groups of registers, a control block, a request priority block, a group of matching blocks, a group of latch registers, a selection register, a priority decryption block. 9 tm . y | 00 00 about

Description

1-12 The invention relates to computing, can be used in the development of processors, the equipment of which is used to transfer data between input-output channels and RAM, and is an improvement to the device by author. St. No. 1190385. The purpose of the invention is to increase the capacity of the device by organizing the possibility of assigning any priority to any I / O channel from the group at the time this channel performs an I / O operation, depending on how the peripheral device organizes the data transfer. Introducing into the device for data exchange between a group of input-output channels by the operational memory, the fixation register group allows setting for each input channel — the output is the priority that is determined by the peripheral device with which the input-output channel establishes communication . The capacity of the latch register is determined by the number of channels in the group. For example, for four channels in a group, the latch register must contain two bits. The maximum number of latch registers that must be in each channel is generally determined by the number of peripherals that can be connected to the I / O channel. However, the number of latch registers can be significantly reduced if one latch register is used for a group of peripheral devices with adjacent addresses, the speed of which for exchanging data with the I / O channel is HLSR. Introduction to the selection register device allows you to select the priority channel itself in order to organize the transfer of data primarily between this channel and the RAM. The size of the selection register is determined by the capacity of the latch register and the number of input / output channels in the group. For example, for four I / O channels in a group, the selection register must contain eighth. bits 7 Introduction to the device of the priority decryption unit allows you to select the most priority channel for organizing the transfer of data between this channel and the main memory. FIG. 1 shows a diagram of an apparatus for exchanging data between a group of I / O channels and random access memory; in fig. 2 is a diagram of a firmware control unit; Fig. 3 is a control block diagram; in fig. 4 is a block matching circuit; in fig. 5 diagram of the priority block of requests; in fig. 6 is a diagram of the priority decoding unit; in fig. 7 is a timing diagram of the execution of the microcommand Memory when the processor accesses it; in fig. 8 is a timing diagram of the microcommand. Memory read from RAM to channels; in fig. 9 is a timing diagram of the execution of the microcommand Write Memory to RAM from channels. A device for exchanging data between a group of input-output channels and random-access memory (Fig. 1) contains a microprogram control unit 1, an input register 2, a memory 3, an output register 4, the first group 5 of AND-OR elements, the first And 6 element , the first trigger 7, the first element AND-NOT 8, the third trigger 9, the second element AND-NOT 10, the second trigger 11, the element OR 12, the second element AND 13, the switch 14, the first 15 and the second 16 groups of registers, block 17 control, request priority block 18, group of matching blocks 19, second group of elements ORI, sync input device 21, group of information inputs - outputs 22) of the device, a group of registers 23, fixing selection register 24, decryption unit 25 priority. The microprogram control unit 1 (Fig. 2) contains a memory of 26 micro-instructions, an address register 27, a micro-register register 28, a decoder 29, a local memory 30, the first 31 and second 32 registers, the arithmetic logic unit 33, the result register 34, the first 35 and the second 36 groups of I-SHS elements, the AND 37 element, the IS-NE 38 element, the first 39 and the second 40 block informational outputs, the block mode input 41, the block gate input 42, the block resolution input 43, the block synchronous input 44, gate 45 output block, address output 46 block, the first information output 47 block, first to third channeling guides sr.otvetstvenno unit outputs 48-50, the output selection unit 51 ki, vyho 52bloka second information, third information input 53bloka. The control unit (FIG. 3) contains 1t data transfer trigger 54, a group of data transfer trigger 55 and 56, the first group of elements AND 57 and 58, the second 59 and the first 60 elements OR, the first 61 and the second 62 elements AND, the element NOT 63, trigger 64 of a data transfer request, trigger 65 of the first transmission cycle, trigger 66 of the intermediate transmission cycle, trigger 67 of the second transmission cycle, group of triggers 68 and 69 of the second transmission cycle of channels, second group of elements AND 70 and 71, group of elements AND-OR- NOT 72 and 73, the first .74 and the second 75 elements are AND-OR, the first group of elements is AND-OR 76 and 77, the second group of elements AND-OR 78 and 79, the first 80, the second 81, the third 82 and the fourth 83 groups of block inputs, the first 84 and the second 85 block inputs, the first to fifth inputs 86-90 blocks, respectively, the first by the third group of outputs 91-93, respectively. The matching unit (Fig. 4) contains data register 94, data buffer memory 95, interface trigger 96, interface buffer selection trigger 97, byte address counter 98, processor buffer selection trigger 99, word number trigger 100, double counter 101 words, the first 102 and second 103 nodes. synchronization, the switch 104, the interface exchange node 105, the data register trigger trigger 106, the register group trigger 107, the register group 108, the opcode 108, the decoder 109, the first 110 and the second 111 groups of elements AND-OR, from the first to the sixth elements AND-IPI 112-117 respectively Actually, the ORI-NE 118 element, the first 119 and the second 120 information inputs of the block, the information input — the output 121 of the block, the input 122 of the block resolution, the synchronous input 123 of the block, the information output 124 of the block, the first 125 and second 126 sync outputs of the block, 127 output of the block , block write output 128, block read output 12. The priority block of requests (FIG. 5) contains from the first to the fourth triggers 130-133, respectively, the priority encoder 134, the storage register 135, the information input 136 and you, the block move 137, the group control control input 138, through which 139-142, the information inputs of the flip-flops 130-133 are connected respectively to the input 138 of the unit, group control output 143; to which the first, second and third outputs of the priority encoder are connected respectively by lines 144-146, group input -147 requests and group output 148 of block requests. Block 18 priority requests works as follows. A group of requests received from a group of matching blocks 19 for group input 147 of requests block 18 of request priority translates to group output 148 of block requests. The group of priority signals, coming from the group input 138 of the block to the information inputs of the flip-flops 130-133, sets these flip-flops to the appropriate states. And the signal arriving via line 39 to the information input of the flip-flop 130 is the highest priority. Since the signals taken from the group control input 138 of the block are accessed asynchronously at the information inputs of the flip-flops 130-133, for the simultaneous installation of these flip-flops, subsynchronization is used by applying sync pulses from the synchronous input 21 blocks to the sync inputs of the triggers 130-133. The outputs of the flip-flops 130-133 are connected to the inputs (first to fourth) of the priority encoder 134, on the first 144 and second 145 outputs of which a two-digit code is formed, which is the address of the highest priority signal of the four-digit word, which goes to the trigger inputs 130-133 For example, if the trigger 130 is set, then from the first and second outputs of the priority encoder, an OO code will be issued via lines 144 and 145, i.e. the address of the first bit of a four-word word. If no trigger 130133 is entered, the third output of the priority encoder is triggered via line 146, which indicates that no trigger 130-133 is cocked. The storage register 135 is used to receive the corresponding clock pulse from the synchronous input 21 of information received from the information input 136 of the block and to output information from the output of the storage register 135 to the information output 137 of the block. The priority decryption unit (FIG. 6) contains six multiplexers 149154, an HE element 155, a decoder 156, a block information input 157 containing lines 158-165. In addition, the firmware control block contains (FIG. 2) the insertion output 166. The forming unit is working as follows: The first to quarterly first multiplexers 149-152 come from the group request 148 of the block request signal from the first channel of the group.The second, third, and fourth information inputs from the first to fourth multiplexers 149-152 From the group request 148 request block signals from the second, third and fourth channels, respectively.The first and second address inputs of the first multiplexer 149 from the information input 157 of the block via lines 15 and 159 are received from the first and second outputs of the selection register with a two-digit code for the channel number for which the highest priority is set up. The first and second address inputs of the second, third and fourth multiplexers 150-152 from the information input 157 of the block are received from lines 3 and 161, 162 and 163, 164 and 165 from the third and fourth In addition, from the fifth and sixth, from the seventh and eighth outputs of the selection register, respectively, two-digit channel numbers for which the second, third, and fourth priorities are set, respectively. Thus, from the output of multiplexer 149, through line 139, the group control input 138 is allocated the highest priority signal that may belong to the first, second, third, or fourth I / O channels. From the output of multiplexer 152, via line 142 to the group control output 138, a signal of the lowest priority is output. The signals from the outputs of multiplexers 149-152 on

neither

The device works as follows.  lines 139-142, respectively, arrive at the group control input 138 of the block and then through the group control input 138 of the priority 18 block 18 requests for the information inputs of the trigger 130-133, Thus, at the first and second outputs of the priority equalizer 134 on the lines 144 and 145 a two-digit code of the number of the most priority signal is obtained, which is formed by the request signals from a group of channels received at the information inputs of multiplexers 149-152; The first, second and third outputs of the priority encoder 134 are through lines 144146 respectively via the group control output I43 of the block enters the group control input 143 of block 25. formation.  The signal on line 146 is fed to the element HE 155, the signal from which is fed to the control inputs of the fifth 153 and sixth 554 multiplexers, allowing the operation of these multiplexers.  The signals on lines 144 and 145 are sent to the two-bit address inputs of an additional 153 and sixth 154 multiplexers.  The first information inputs of the fifth 153 and sixth 154 multiplexers are received via lines 158 and 159, respectively, from the first and second outputs of the selection register 24.  The second, third and fourth information inputs of the fifth 153 and sixth 154 multiplexers are received via lines 160 and 161, 162 and 163, 164 and 165 signals from the third and fourth, fifth and sixth, seventh and eighth outputs of the selection register 24, respectively.  The outputs of the fifth 153 and sixth 154 multiplexers are connected to the first and second inputs of the decoder 156.  Thus, an address signal appears at one of the outputs of the decoder 156.  The signal at the first output of the decoder 156 is a request from the first channel; on the second - from the second channel; on the third - from the third channel; on the fourth - from the fourth channel.  The information received from the outputs of the decoder 156 is received via the synchronization signal into the storage register 135 and then this information is transmitted via the information output 137 to the control block 17. There is a matching block 19, a data buffer 95, which has two data fill zones.  The capacity of each of the zones corresponds to the size of the RAM.  In this case, it is equal to a double word.  The width of the buffer memory corresponds to the width of the information path of the processor, which in this case is equal to one word and through the paths of which the channel exchanges data with the RAM.  The operation code executed by matching unit 19 is in operation code register 108.  The signal from the second output of the decoder 109 determines that a write operation is performed in the matching unit.  The signal from the first output of the decoder determines that a read operation is performed in the matching unit.  .  When reading is performed, data from the peripheral device is byte-byte from the information input - output of the matching unit 19 via the switch 104 being transferred to the data register 94.  From the data register 94, through the first group of 110 AND-OR elements, the data is recorded in the buffer memory 95 data at the output from the second group 111 of the AND-OR elements.  If the group trigger 107 is reset, after accumulating a double word of memory, the first word is first read from the buffer memory and transmitted through the information output of the matching unit, the second group 20 of AND-OR elements, the first group 15 of registers to the second group 16 of registers then read the word and transfer it to the first group of 15 registers.  After the registers are filled, the trigger is set to one. hers 107 is occupied by a group of registers.  To determine the reading in this case, the third element AND-OR 114 generates a request for data transfer which, through the output of the request of the matching unit 19, arrives at the input of the request priority unit 18.  During a write operation, during the second data transfer cycle of the corresponding channel, a trigger group 107 is set by a signal received at the resolution input of the matching unit, registering the presence of data received from the main memory into the first 15 and second 16 registers of the corresponding channel .  If one of the zones is free in the data buffer memory 95, the first data word from the second group of registers 16 and then the second data word is transferred through the second information input of the matching unit 19, the first group 110 of the AND-OR element to the buffer memory 95 data.  Data from the buffer memory 95 data through the second information input of the switch 104 enters the data register 94, from where they are output to the information output of the matching unit under the control of the exchange node 105 via the interface and the data register trigger 106.  During a write operation, the request for data transfer is established using the third AND-OR 114 element if the trigger 107 for the group of registers is cleared.  The read operation signal from the first output of the decoder 109 and the write operation signal from the second output of the decryptor 109 are supplied respectively via the read outputs 129 and 128 records of the matching unit 19 to a group of 20 I-NLs controlling the load direction of the first 15 and second 16 groups of registers, and on control block 17.  An interface access trigger 96 is used to control the data buffer addressing.  If the interface reset trigger 96 is reset, data exchange between the buffer data memory and the address register group, the buffer memory to the double word zone is performed using the processor buffer trigger 99, and before the word using the word number trigger 100.  The word number trigger 100 during the transmission of the double word is switched.  If the interface access trigger 96 is set, then an exchange between the buffer memory 95 data and the data register 94 can be performed.  of  In this case, the zone is addressed using the interface selection buffer trigger 97, and the words and bytes inside the word are triggered by the byte address counter 98.  A two-bit double word counter 101 indicates the number of double words in the buffer. memory 95 data.  During the write operation, it shows the number of empty double words 1 in the buffer memory 95 data, during the read operation the number of filled double words. At the beginning of the write operation the counter is set to 2 (two double words not filled) and during the transfer of the double word from register groups 15 and 16 are decreasing.  After transmitting a double word through an interface, the double word counter 101 is enlarged.  At the beginning of the read operation, the counter is set to O and is modified accordingly when exchanging data.  The operation sequence of the equipment of the matching unit 19 during data transfer between the buffer memory 95 of the data and the register 94 is performed using the second synchronizer 103.  Transmission between data buffer memory 95 and register groups 15 and 16 is controlled by the first synchronizer 102.  The first synchronizer 102 generates the load gates of the first 15 and second 16 groups of registers of the corresponding channel, which are received respectively when transferring data to the buffer memory or from the buffer memory to the first and second synchronization inputs of the matching unit 19.  Run the second syn.  about. gasator 103 is produced via e.  V ent AND-OR-NOT 118, and the launch of ne, th synchronizer 102 through n and the element AND-OR 116.  Requests from all the matching blocks 19 are sent to the request priority block 18 and then with the help of the selection register 24, the priority block is determined by the formation block 25 and transferred from the block 18 to the control block 17, in which the data transfer trigger 54 is set and one of the group of data channel triggers 55 and 56, which indicate which matching unit 19 will exchange data.  The input of block 17 is managed and the second group of inputs from matching blocks 19 receives an operation code that is used for instrumental generation of a microcommand for memory access on the first group of elements 57 and 58 and in the element OR 59, the output of the second microcommand enters to the input of the mode of the microprogram control block 1, to the register 28 micro-commands 7 through the first group of 35 elements -OR.  In this case, the potential from the data transfer trigger 55 of control unit 17 blocks the reception of micro-commands from memory 26 of micro-commands of microprogram control unit 1 on the first group 35 of AND-OR elements and passes a command from control block 17, during which the data must be exchanged between operational memory Tew and the first 15 and second 16 groups of registers through the internal paths of the processor.  To control the data flow, the control unit 17 generates a sequence of signals from the output of a data request trigger 64, a trigger 65 for the first transmission cycle, an intermediate transmission cycle trigger 66, a second transmission cycle trigger 67, and for control of the first 15 and second 16 groups of registers from the outputs of the first group elements AND-OR 76 and 77 and the second group of elements AND-OR 78 and 79.  The microcommand Memory is executed in two cycles.  In the first cycle of the memory, the data address is prepared and in the case of writing to the memory the recorded data.  The reading and writing is done in the pause between the first and second cycles.  The length of the pause depends on the time it takes to access the memory.  This time is much longer than the first and second memory cycles.  In the second cycle of memory, in the case of reading, data from the memory and transfer through the internal paths of the processor to the first 15 and second 16 groups of registers are selected.  A data request request trigger 64 of block 17 is used to start the cycles of the hardware-formed microcommand Memory, Request Priority Block 18, as well as the selection register 24 and generation block 25 are designed to select the most priority channel.  The switch 14 is designed to select data from the main memory or the register 34 of the result of the firmware control unit 1 and is a group of ORS elements.  In the timing diagram (FIG.  7) the operation of the device for data exchange between a group of iRODE channels and random access memory for execution of the microcommand. When the processor is accessed by the processor, the following symbols are used: d- synchronization; Taking in the first register 31 addresses of the RAM; 6- reception of the double data word in the output register 4; I write to the local memory 30 of the modified address of the operational memory; 5- issue of the first word, given from the first group of 5 elements AND-OR; e- output of the third trigger 9 mc: - outputting the second data word from the first group of 5 AND-OR elements; control switch 14 to select data from the main memory; and - for writing the first word of the data; k - write the second data word.  A device for exchanging data between a remote channel group. input, output, and RAM to execute a microcommand. When a processor accesses it, the processor works as follows.  From the memory 26 of the micro-commands of the microprogram control unit 1, the address from the register 27 of the address through the first group of 35 AND-OR elements is entered into the micro-command of the microcomputer register 28 by the decoder 29, from the seventh output of which the local memory 30 is fed the address by which The first register 31 reads the address of the RAM data, which through the address output 46 of the microprogram control unit 1 is fed to the address output of the RAM.  The double word data from the RAM is entered into the output register 4, from which the first data layer is fed to the switch 14 using the first group of 5 I-IL elements. .  The selection of a new word is controlled by the first AND-NE 8 elements according to the established first trigger 7, which is established via the first element / AND 6, by the least significant bit of the double word address from the first register 31 of microprogram block 1. management  The address of the RAM data is also supplied to the arithmetic logic unit 33, where it is modified and through the result register 34 and the switch 14 is recorded in the local memory 30.  After that, the control of the switch 14 at the output of the second element And 13 is switched to the selection of the first word of data from the operational memory.  After writing the first data word, the second output of the decoder 29 of block 1 sets the third trigger 9, which inverse output on the first element And 6 changes the low bit of the address of the working memory, which is stored at the end of the execution of the microcommand Memory on the first trigger 7 and through the first element The IS-NE 8 changes the control of the first group 5 of the AND-OR elements to output the second data word from the output register 4 to the switch 14, and the direct output of the third trigger 9 controls the transmission of this data word through the switch 14 against the background of For the next firmware.  In the timing diagram (FIG.  8) the operation of the device for exchanging data between the I / O channel group and the RAM for performing the micro-command of the microcommand. Memory read from the main memory is used the following symbols: a - synchronization; B - trigger output 65 of the first transmission cycle; 6 output trigger 66 intermediate transfer cycle; g - trigger output 67 of the second transmission cycle; 3 reception in the first register 31 of the memory address and byte counter; e - receiving a double data word in the output register 4; eq - issue of the first data word from the first group of 5 AND-OR elements; 3 issuance of the second data word from the first group of 5 elements AND-OR; , h - the output of the second trigger 11 ;.  K - control switch 14 to select data from RAM; l - record in the local memory 30 of the modified address memory memory and byte counter; m-strobe of the first group of 15 registers; n - the gate of the second group of 16 registers.  A device for exchanging data between a group of channels and RAM for reading data from RAM into the first 15 and second. 16 groups of registers works as follows.  From control block 17 to microprogram control block 1, micro-command register 28 is entered into an instrumented micro-command that goes to decoder 29, from the seventh output of which the local memory 30 is fed to the first register 31 in the first cycle of memory is read Dfic data of the RAM, which is supplied to the address input of the RAM, and to the arithmetic logic unit 33, on which it is modified.  From the memory into the output register A, a double data word is read.  The low-order bit of the RAM address, addressing the first data word from the first register 31 of block 1 through the first element AND 6, sets the first trigger 7, which through the first AND-NO element 8 controls the selection of the first data word on the first group of 5 AND-OR elements which arrives at the switch 14.  From the output of the data transfer trigger 54 of the control unit 17 to the information input of the second trigger 11, a signal is set that sets this trigger at the beginning of the first cycle of the Micro Memory command. The second trigger 1 1 controls the transfer of the first word of RAM data through the switch 14 through the second group of 20 I-YAL elements under the control of the write output of the matching unit 19 and through the first group 1 of registers, since a constant gate is applied to the synchronizing input and latched in the second group 16 registers with the coffin formed on the first group of elements AND-OR 76 and 77 of the control block 17 by signals from the output of the group of flip-flops 55 and 56 of the data transmission channels of the flip-flop 67 of the second transmission cycle and synchronization signal the memory on the first register 31 is read by the byte counter, which indicates the amount of bytes that remains to be transferred from the operational; memory channels.  The byte counter is transmitted to the arithmetic logic unit 33 on which it modifies c.  After resetting the second trigger 11, the control of the switch 14 is switched to issuing from register 34 the result of the modified address, which is recorded in the local memory 30 Then on the second AND-NE element 10 according to the signal from the output of the trigger 67 of the second transmission cycle of block 17 and the signal from the synchronous input 21 of the device, a signal is generated which is fed to the second input of the first element NAND 8 and inverts the outputs of this element.  Thus, the first group of 5 AND-OR elements selects the second data word, which through the switch 14 under the control of the signal from the output of the second element AND 13 enters through the second group of 20 AND-OR elements to the first group of 15 registers, where it is latched along the gate, formed on the second group of elements AND-OR 78 according to the signals from the output of the group of trigger data 55 and 56 for the transmission of channel data, the clock signal and the output signal for the group of trigger elements 68 and 69 of the second channel transmission cycle, Recording the modified counter from the register 34 of the block result 1 to the local memory 30 is performed against the background of the following microcommand.  In the timing diagram (FIG.  9) the operation of the device for exchanging data between the I / O channel group and the operational memory for executing an instrumented command. The following symbols are used in the operational memory: p-synchronization; 8- trigger output65 of the first transmission cycle; & - output of the intermediate transfer trigger 66; d - reception in the first register 31 of the memory address; d the reception in the second register 32 of the data from the second group of 16 registers; e- receiving data in input register 2; ls-strobe second group 16 registers; Record in the RAM.  A device for exchanging data between a group of I / O channels and random access memory for writing data from the first 15 and second 16 groups of registers into the operational memory works as follows.  From the second information output of the group 16 of registers to the firmware control block to the second register 32, through the second 36 group of AND-OR elements, under the control of the signal from the output of the data transfer trigger 54 of the control block 17, the first gate data word is received from the output of the first AND-74 block 74 17, which is processed on a clock signal.  After receiving the first word in the second register 32 of block 1, the data is transmitted through the first information output 47 of block 1 to input register 2, where they are received via a gate formed on the second AND-OR element 75 of block 17, which B1 is abated by a sync signal and a third control output of block 1 After receiving the first data word in input register 2, the second data word from the first group of 15 registers is rewritten into the second group of 16 registers by strobe from the output of the first group of elements AND-OR 76 and 77 of block 17, generated from the output signals Trigger groups 55 and 56 of the data transmission of trigger channels 65 of the first transmission cycle and clock signal.  From the output of the second group of 16 registers, the second data word is recorded in the second register 32 of block 1 via the second group of 36 I-IPI elements along the gate from the output of the first AND-OR element. 74 of the block 17 generated by the signals from the output of the data transfer trigger 54, the trigger 65 of the first transmission cycle and the sync signal. From the output of the second register 32 of block 1, the second word data is sent to input register 2, on which it is latched along the gate from the output of the second element AND-OR 75 of the block 17, 1 formed on the signals from the output of the trigger data and the clock signal.  From the local memory 30 of block 1, the address is read, which through the first register 31 is transferred to the address output of the RAM. On the first output of the decoder 29, the block 1 on the AND 37 element generates (; write strobe into the RAM, which is fed into the RAM 3  A device for exchanging data between a group of input-output channels and random-access memory to select and assign an appropriate priority to an input-output channel from a group of channels that have made requests for organizing data transfer between a group of channels and random-access memory, works as follows.  When a specific configuration of peripheral devices is connected to a group of I / O channels on a group of latching registers 23, manually, (or in some other way) using information switches for each peripheral device connected to the corresponding input / output channel, the information is defined a two-bit word and which prioritizes an I / O channel if this channel communicates to exchange data bytes with peripherals m device.  For example, if you take the combination of two bits as word 00 as priority 1 (highest priority) and 11 as the priority 4 (lowest), then if to connect the peripheral 16th device to the address with the I channel, the highest priority is needed with respect to the other channels of the channel group, the two-bit code 00 is fixed in the sixteenth two-bit latch register 23 belonging to the 1st channel.  This means that if the 1st channel starts communication for data exchange with the peripheral 16th device, then for the 1st channel the highest priority is set.  Setting the appropriate priority for any I / O channel from a group of channels is performed as follows.  During the execution of an I / O command (before establishing a logical connection between the channel and the peripheral device), the firmware determines the priority of the channel on which the input command is to be executed — and / and. The established priorities of all previously started channels from the I / O channel group that have not yet completed communication with peripheral devices are modified.  If the priority of the newly launched channel does not intersect with the priorities of the previously started channels, then: if the priority of the newly launched channel is free and if this channel does not work, the priority for the given channel is assigned and the execution of the command / input-output pred.  in the standard way; if the priority of a newly started channel is lower than or equal to the priority of the same previously started channel, then the old priority of this channel is maintained. The output of the output output card continues in the standard way, if the priority of the newly started channel is higher than the priority of the same previously started channel, and the execution of the input - output command continues with standard braz.  If the priority of the newly started input-output channel intersects with the priority of one of the previously started input-output channels, then: if there is a free higher priority, then this priority is assigned to the newly started channel and the execution of the input-degenerate command continues, in a standard way; if all higher priorities are occupied, then the execution of the I / O command is terminated and a result indication is generated that indicates that the channel is busy.  At that, the condition is remembered that after the I / O channel, the priority of which turned out to be the same as that required for the newly started channel, terminates the started communication with all peripheral devices, the I / O command will be re-executed via the previously unsuccessful channel input - output.  When the I / O command is re-executed, the described firmware priority assignment to the newly started I / O channel is repeated.  Consider the assignment of priority for a particular I / O channel during execution. an I / O command, which indicates the channel number (for example, Wth) and the address of the peripheral device (for example, 13th) with which the channel is to communicate with in order to transfer data, the firmware determines the priority of the 3rd channel, which it needs to be installed in order to organize the correct transfer of data between the 3rd channel and the 13th peripheral device.  For this purpose, the microcommand interpreted on de-pyfrarator 29 (the signal from the eighth output of the decoder, which valve the fifth input of the AND-OR group 36), from the thirteenth fixation register 23 belonging to the 3rd channel, reads the two-digit code which is via the third information input 53, the sixth input of the AND-OR group 36 in the standard way through the first register 31, the arithmetic-logical node 33, the result register 34, the second control output 52 of the program control unit 1, through the controller 14 first information the input 39 of block 1 is stored in a special cell (for example, cell 1} of local memory 30 and is stored there.  According to the following micro command, interpreted on the decoder 29 (the signal from the ninth output of the decoder 29, which valves the AND-OR element of group 36 on the seventh input), the eight-input code AND is read from the selection register 24 from the selection register 24 -OR group 36 is stored in a standard way in a special cell (e.g., cell 2) of the local memory 30 and is stored there.  After reading the information from the latch register 23 and the select register 24, the tests necessary for the assignment of the appropriate priority for the 3rd channel are performed by the firmware.  For this purpose, information is used on which input / output channels from the channel group were previously started and how many peripheral devices were running on each channel.  This information is placed in special local memory cells, such as cell 3, whose four tetrads addressed by channel number (00 is the tetrad for channel 1; 11 is the tetrad for channel 4) are used to determine the activity of each channel in depending on which priority it is assigned to (the bit in the tetrad with address 00 indicates that the channel is working with the highest priority, bit c.  a tetrad with address 11 - with.  lower priority).  For example, in cell 4, the four bits (counter) of which determine how many peripheral devices are started for each channel, byte with address 00 for the 1st channel, byte with address 11 for the 4th channel.  Assume that the two-digit code read from the 13th fixation register 23 is 01, t. e.  For channel 3, you must assign a priority equal to 2.  Before . assign the 3rd channel priority 2 it is necessary to determine whether one of the channels of the channel group is working with this priority or not.  For this purpose, cell 4, where the contents of selection register 24 is stored, which determines which channel with which priority it operates (the zero and first bits with addressing 00 determine the output priority of the channel, which number is written in these bits; the sixth and seventh bits with address 11, the lowest priority of the channel whose number is written in these bits is determined by the address that is determined by the priority for the 3rd channel, t. e.  at address 01, the second and third bits of the contents of the selection register 24 are allocated.  For these bits, which are the channel number from cell 2 of the local memory, the corresponding tetrad is selected, in which the activity bit corresponding to priority 2, t is analyzed. e.  activity bit with address 01.  Depending on the result of the analysis, the following actions are performed.  one. The channel whose number is specified in the second and third bits of the contents of the selection register 24 does not work.  The analysis of all bits of tetrad activity for the 3rd channel is performed.  A. Channel 3 is not working.  In the second and third bits of the selection register 24 (the cell of the 4th local memory), the number of the newly started channel 10 is entered, which indicates that priority 2 is assigned to the 3rd channel; in the tetrad - (the cell of the 3 local memory) for the 3rd channel the bit at address 01 is set to I, t. e.  Channel 3 is becoming active in priority 2; 1, t is added to the counter at address 10 (cell 4 of the local memory) belonging to the 3rd channel. e.  it is recorded that one peripheral device is running on channel 3.  B.  The 3rd channel is working, and its priority is higher or equal to the priority of the newly launched 3rd channel.  The priority of the 3rd channel does not change.  1 t is added to counter 3 (address 10). e.  it is recorded that another peripheral device is running on channel 3.  B. The 3rd channel is working, and its priority is lower than the priority of the newly launched 3rd channel.  Channel priority is set to new.  The activity of the 3rd channel according to the old priority is removed and the activity of the 3rd channel with the assigned priority 2 is set.  Counter 3 (address 10 is added 1, m. e.  it is recorded that another channel has been launched on the 3rd channel. peripheral device.  2 The channel whose number is indicated in the second and third bits of the contents of the selection register 24 is working.  Channel 3 is not working.  In this case, it is analyzed whether there are free, higher priorities, in particular, whether priority 1 is free.  This is accomplished by analyzing the activity of that channel, whose number is determined by the contents of the zero and first bits of the selection register 24 (cell 2 of the local memory).  BUT.  No channel with priority 1 is working, the number of the newly started channel (10) is entered in the zero and first bits of the contents of the selection register 24, which indicates that the 3rd channel has priority 1; in tetrad 3, at address 00, the 3rd channel activity bit is set, t. e.  Channel 3 becomes active in priority I; 1 is added to the counter of the 3rd channel. e.  it is recorded that one peripheral device is running on the 3rd channel.  B.  One of the channels with priority I is working.  The execution of an I / O command is terminated.  A result sign is formed microprogrammatically, which indicates that the 13th peripheral device cannot be started on the 3rd channel.  At the same time, information is stored in the local memory that on channel 3 with priority 2, the execution of an I / O command was unsuccessful.  This information is further analyzed each time one of the channels of the I / O channel group is released.  If the channel that has completed its operation has priority above or the same (in this case, priorities 1 or 2), then an interrupt is formed on the 3rd channel, which re-attempts to launch the 13th peripheral on the 3rd channel.  The information stored in the local memory about the unsuccessful attempt to launch the 13th peripheral device on the 3 MHz channel is destroyed.  3  The channel whose number is indicated in the second and third bits of the contents of the selection register 24 is working.  Channel 3 also works.  In this case, the set priority for the 3rd channel is analyzed.  This is accomplished by detecting in the tetrad 3 the address of the set bit of the 3rd channel activity (the cell of the 3 local memory).  A, For the 3rd channel, the same or higher priority is set than the TOTj that is required for the newly launched peripheral device on the 3rd channel.  In this case, 1, t is added to counter 3 (cell 4 of the local memory) of the 3rd channel. e.  fixed; that one more device was started up on channel 3.  B.  The channel has a lower priority than the one required for the newly launched 13th device over the 3rd channel.  It is analyzed whether a higher priority is free than that which is required for the newly launched 3rd channel (in the present case, priority 1. ) If it is free, priority 3 is assigned to channel 1, the activity bit but the lower priority is cleared and the activity bit 3 of the GO channel in tetrad 3 according to priority 1 is set.  If priority 1 is occupied, executes subsection B of item 2 described above.  After assigning the desired priority to the 3rd channel, the contents of the selection register 24 from the cell 2 of the local memory 30 are recalled to the selection register 24.  The transfer is performed in the standard way through the AND-OR element of group 36 and then through the first register 31, the arithmetic logic unit 33, the result register 34, the second controlled output 52, the switch 14, from which the PS information is output to the tenth output The decoder 29 through the code entry 166 is written to the selection register 24.  After assigning the required priority to the input-output channel and recording information in the selection register 24 and in the case, when no requests from the input-output channel group originate, data exchange with the operational memory selects the channel with the highest priority at the current time. channels are performed on multiplexers 149-152 by providing control signals from the zero and first outputs of periicTpa 24 of choice to the address input of the multiplexer 149 on lines 158 and 159; n and the address input of the multiplexer 150 along lines 160 and 161 is from the second and third outputs of the selection register 24; to the address input of the multiplexer 151 with lines J62 and 163 from the fourth and fifth outputs of the register 24 of choice; to the address input, multiplexer 152 via lines 164 and 165 from the sixth and seventh outputs of the selection register 24.  Thus, the request signal from the output of the multiplexer 149 (line 139) always has the highest priority, and the request signal from the output of the multiplexer 52 (line 142) always has the lowest priority. In block 18, the priority of requests is selected in the standard way. requests for sinful input-output channels, with the help of triggers 130-1 33 and the priority encoder 134.  In this case, the first and second outputs of the priority encoder 134 remove the number of a, r, ny from the multiplexer OE 149-152, the link from which at the time of the request for trigger 130-133 but for the sync pulse of the sync input to the synchronous inputs of the trigger 130- 133 of the sync source 21 5 is the highest priority. To determine which input: AO is the highest priority request, two multiplexers 153 and 154 and a decoder 156 are used.  The first inputs of multiplexers 153 and 154 are supplied by lines 158 and 159, respectively, of the channel that is fed to the address inputs of the multiplexer 149, to the second inputs of multiplexers 153 and 154, respectively, by the number of that channel that is fed to the address input of the multiplexer, etc. d.  Thus, with.  outputs are tippee. The channels, 1 53 and 154, take the number of that channel, the request of which is currently the highest priority.  This sanal number is decrypted -1 on-decipher 156, one of which is removed from the request signals; from the first output - for the first channel, from the second output - for the second channel and t, d.  These requests are remembered by a sync pulse in storage register 135, from which output requests for information output 137 are received in control unit 17 and processed there in the standard way.  Ph o r y Device for exchanging data between a group of input-output channels and

operative memory by aut. St. No. 1190385, characterized in that, in order to increase the capacity of the device by organizing the possibility of assigning any priority to any I / O channel from the group at the time of this cannon I / O operation, a group of latch registers, a selection register, a priority decryption unit, moreover, the outputs of the group latching registers are connected to the third input of the logic conditions of the firmware control block, the output of which is written to the

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Claims (1)

and gaining A device for exchanging data between a group of input / output channels and · RAM memory according to ed. St. No. 1190385, characterized in that, in order to increase the throughput of the device by organizing the possibility of assigning any priority to any I / O channel from the group at the time of this I / O operation, I entered a group of latch registers, a selection register, a priority decryption block, moreover, the outputs of the registers of the fixing group are connected to the third input of the logical conditions of the microprogram control unit, the output of which is connected to ^ 1 . four- . one CHYAUG ... 1 Λ from l * “ ^J .5 the input of the recording of the selection register, the information input of which is connected to the output of the switch, the second input of the logical conditions of the microprogram control unit is connected to the output of the selection register and to the information input of the priority decryption unit, the information output of which is the input of the grouping of control outputs and inputs of the priority decryption unit respectively connected to the information block of the priority of the requests, the outputs of the request, the group of control inputs and outputs of which are connected with the group of input of the request, the group -