SU1183962A1 - Analog-digital differentiator - Google Patents

Description

The invention relates to automation and computing and can ¹ be used, in particular, in the construction of digital measuring, control devices operating 5 in real time.

The purpose of the invention is to improve the accuracy of the formation of the derivative and reduce hardware costs.

The drawing shows a block diagram of the analog-digital differentiator.

Analog-digital differentiator; contains tracking analog-to-digital converter 1, shift register 2, the first and second elements are NOT 3 and 4,. > 5, the first and second elements OR 5 and 6, the result counter 7 (of the reverse type), the generator 8 clock pulses,. ow and from the first yo the fourth elements 9–12. The generator 8 forms 20 two pulse sequences with the same repetition rate: the main one at the first output and delayed by / half of the clock frequency at the second output, 25

'Differentiator works as follows.

With the appearance of the signal at the installation input, the initial setting of the counter of the tracking 30 analog-digital converter 1 and counter 7 is made to "0", the initial value 010101 ,,, 01 is entered into the shift register 2, the analog input signal is fed to the information input of the tracking anode-digital converter 1, it converts it into a sequence of binary-coded increments, the magnitude of which is determined by the sign of the error signal in the servo to the analog-to-digital converter, that is, the positive increment represents Xia logic-one level, and the negative - logic-zero level. Binary coded increments 45 arrive at the information input! ¹ register 2 shift, as well as the first input element And 9 and through the element NO 3 - the second input element X 10 "

On the other inputs of the elements And 9 and 10 at 50 step pulses from the first output of the clock generator, which allow the passage of positive

increments through the elements AND 9, OR 5 to the summing input of counter 7 or allow the passage of negative increments through the elements AND 10, OR 6 to the subtracting input of counter 7. During the first N cycles of the clock pulse train (Ν-bit width of the shift register 2) at the register output 2 shifts are formed alternating "0" and "1" initial values previously recorded in the "shift register 2". These values are received at each clock cycle of a delayed series of clock pulses at the inputs of the reversible counter: the signal "0" through the elements HE 4, AND 12, OR 5 to the summing input of counter 7, the signal 'Ί ”through the elements AND 11 and OR 6 to the subtracting input of the counter 7. The initial value in shift register 2 is chosen so that the algebraic sum of increments received only from the output of shift register 2 to counter 7 during the first N cycles of the delayed clock series is zero.

Thus, to (Ν + 1) -th cycle of the device operation, the contents of the counter Ί are equal to the algebraic sum of the increments received from the output of the tracking analog-digital converter 1. Starting from the N + 1 clock cycle of the clock generator of the generator, 8 clock pulses at the output of the shift register 2 appear delayed binary-coded increments that pass on each clock of the delayed clock pulse series: Positive increments through AND 11, OR 6 elements - to the subtracting input of counter 7, negative ones through the HE 4, AND 12 and OR 5 elements - on the sum uyuschy input of the counter 7. At each step the series of timing pulses is performed in the algebraic summation of increments down counter 7, and at each cycle of the delayed clock pulse series - algebraic summation delayed N cycles at increments with the opposite sign. Thus, a tracking mode for computing a numerically derived derivative of the input analog signal is achieved.

1183962

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Claims (2)

ANALOG-DIGITAL DIFFERENTIATOR, containing a tracking analog-to-digital converter, whose information input is the input of the differentiator, and the clock input is connected to the first output of the clock generator, two elements OR and a result counter, the output of which are the outputs of the differentiator, which is equivalent to the fact that increase the accuracy of the formation of the derivative and reduce hardware costs, it contains two elements NOT, four elements AND and a shift register connected by an information input to you Odom increments tracking analog-digital converter, a first input of the NOR and the first input of the first AND gate, a timing input - to the first output of the clock, a second input of the first AND gate. and the first input of the second element And, and the output with the input of the second element NOT and with the first input of the third element And connected by the second input to the second output of the clock generator and the first input of the fourth element And connected by the second input with the output of the second element NOT, but output with the first input of the first element OR connected by the second input to the output of the first element AND, and the output to the summing input of the result counter connected by the subtracting input with the output of the second element OR connected by the inputs. to the outputs of the second and third elements And, and the second input of the second element And is connected to the output of the first element NOT. 51) ,,,, 1183962 > one 1183962 2