SU1170614A1 - Multidigit logarithmic analog-to-digital converter - Google Patents

Abstract

MULTI-DISCHARGE LOGARIFIC, KIY ANALOG-DIGITAL CONVERTER, containing a synchronization unit, a buffer stage, a main comparator, two sources of reference voltage and ifformators of the discharge, each of which contains a series-connected amplifier and analogue storage device, comparator, the output of which is connected the information input of the memory trigger, the output of which is connected to the input of the control gain of the amplifier and the information input of the shift register, the first input of the comparator p Connected to the output of the first voltage source, the control input of the analog storage device is connected to the reset input of the memory trigger and one output of the synchronization unit, the buffer stage has a series-connected buffer amplifier and a buffer analog storage device, the control input of which is connected to the control the input of the analog storage device of the first form of the discharge body, the first input of the main comparator is connected to the output of the second reference voltage source, o t l and h y and j {so that, for the sake of simplicity, an input key has been entered into the discharge driver, the output of which is connected to the output of the analog storage device; and the input of the amplifier, the output of the latter is connected to the second input of the comparator and the input of the input key of the subsequent bit driver, two keys are entered into the buffer W cascade of the converter, the output of the first if3 them is connected to the output of the buffer analog storage device and the input of the buffer amplifier, the output of which is through another the key is connected to the input of the amplifier of the second driver of the discharge, the input of the converter is connected to the input of the input switch of the first form converter, the input of the first switch O) of the buffer stage and the second The first input of the main comparator connected (the OUTPUT to the trigger input of the synchronization unit, the other outputs of the synchronization unit are connected to the corresponding control inputs of the input keys of the first and second bit drivers and the output of the second key of the buffer stage are output. single outputs of the converter.

Description

The invention relates to radio electronics and computer technology and can be used in high-speed converters with a logarithmic characteristic. The purpose of the invention is to simplify a multi-bit logarithmic analog-to-digital converter. The drawing shows a functional diagram of a multi-bit logarithmic converter. The multi-bit logarithmic analog-to-digital converter contains synchronization unit 1, buffer cascade 2, main comparator 3, first 4 and second 5 sources of basic voltage, discharge drivers, amplifiers, analog storage devices 8y-8j ,, comparators 9, -9, memory triggers, shift registers 11, -1T, buffer amplifier 12, input keys 13, -13, buffer analog storage device 14, first 15 and second 16 keys. The transfer coefficients of the amplifiers are D, D, ..., D, respectively. The first source of reference voltage is equal to the maximum value of the voltage to be transformed. The second source of reference voltage 5 is the threshold of the main comparator 3 used to divide the dynamic range into two subbands. Such a division is intended to eliminate the effect of the dielectric absorption of capacitors used in the analog storage units 8, -8. The reference voltage source -5 is chosen less and. / K () ,, g where and, the minimum signal to be converted, K - coefficient di: electrical absorption of capacitors. The synchronization unit 1 generates control signals C1, C2, C3, U1, U2, T1, T2, TZ. Multi-logarithmic analog-to-digital converter works as follows. When the T1 signal appears, the first switch 15 closes, the analog 8 / j and the buffer 14 analog storage devices operate in the voltage sampling mode, the memory trigger 10, j is set to one, resulting in the amplifier 7 operating in the voltage follower mode. Depending on the state of the main comparator 3, according to the control signals U1 I-U1, the input key 13 closes if the signal to be converted is less than the reference voltage of source 5 or the first key 15 opens in the case when Od is not less than the reference voltage of source 5. In case when Ujf is not less than the reference voltage of source 5, the converted signal Uy passes through the first switch 15 and the buffer amplifier 12 and is stored in the buffer analog storage device 14. At the same time, zero potential is applied to the input of amplifier 7 th memory 8 is zero. After termination of the control signal T1, the first key 15 and the input key 13 are opened, and the buffer analog storage device 14 and analog storage device 8 (switch to storage mode. The voltage from the output of the buffer analog storage device 14 and analog storage device 8 | arrive at the inputs of the buffer amplifier 12 and amplifier 7, respectively, and the trigger of memory 10 is set to zero, which leads to the operation of amplifier 7 with a transfer coefficient equal to 1. Since UU / K ", then from X rtiQjr There is no control signal C / to record the state of comparator 9u in memory trigger 10 /, therefore the state of memory trigger 10 / remains unchanged. When the TK control signal appears, shift in the shift register 11 |,., And writing the state of the memory trigger 10 in the shift register 11jj., the second key 16 closes when the input key 13j is open, the analog memory device 8 is working. melts in the sampling mode, the memory trigger 10 is set to one, I, which determines the operation of the amplifier Tu in the voltage repeater mode. As a result, the signal to be converted and, stored in the buffer analog storage device 14, passes through the buffer amplifier 12, the second switch 16 and the amplifier 7.J with a transfer coefficient equal to the current moment, and stored in the analog storage device Bg. After the termination of the control of the TZ, the second switch 16 opens 31, the analog storage device 8 switches to the storage mode. The memory trigger 10 2 is set to the zero state, that. causes a single gain of amplifier 7, the voltage stored in analog storage device 8, is fed to the input of amplifier 7. According to the control signal T1, bit driver 6 and buffer stage 2 are reset to sample the next value of the signal to be converted. the control unit of the synchronization unit 1 for the bit generator 6 coincides with the control signals for the stage of the bit shaper 6,., for the shaper 6 y-, with the control signals of the bit shaper 6i and so on. . In the case when Uj is less than the reference voltage of source 5, the procedure occurs, similar to the previous case, with the only difference being that the input key 13f. Is closed to store the converted signal Uj (in analog storage device 8, / when supplying corresponding control signals. In this case, after the termination of the control signal T1, the output of the amplifier is set to voltage (/ 2 U, U, D, which is compared by comparator 9f with the reference voltage of the first source of reference voltage 4, equal to max P The control unit C2 in the memory trigger of bit 10 stores the state of comparator 9 which is equal, with (and .. D) S and. ill, with (.i, B as a result of the gain of the amplifier 7 (/ is determined by the state of the memory trigger bit 10, and the output voltage of amplifier 7 is equal to O) and (2) J / 2 / J / 2 for (UyDpiUp ,; Ux for () and. Thus, the highest bit is set. Unlike In the previous case, the key 47, in the expanded state of the second U4 key 16, as a result, in the analog storage device 8, is stored. The output terminal voltage ate "7, defined by a through (3). For both cases, the input of the 7n detector at the time of the T1 control signal supply is supplied with a voltage equal to the metering (3) Pack - // g U, U, D, while the output of the 7l amplifier sets the voltage f / 2. D which is similar to the first shape of the bit body 6 is compared by the comparator 83. with the reference voltage 4. By the control signal CT in the memory trigger of bit 10, the state of the comparator 9, 0, and, Jo is remembered. 1 IJ1 l, at and „o (g. After that, a voltage equal to (4), (5) and (6) and.and / ng / 2-„ -g / 2 Thus, the second bit of the converter is developed. When the control signal T2 is applied, the key 13 closes, the memory trigger of the bit 9 is set to one, and the amplifier 7 operates in the voltage repeater mode and the analog memory 8j remembers the voltage , defined by (7), etc. Further, the same procedure occurs as in the discharge former 6, and in subsequent cascades a Similarly, the work of the bit shaper 6. TiaK as the volume of the shift registers is reduced by 1 in the direction of the lower bits and the transfer coefficients of the controlled amplifiers are set in accordance with the logarithmic scale, information about the code of one sample corresponding to the logarithmic From the description}, it is clear that the main comparator 3 divides the dynamic range of the converter into two sub-ranges, as a result of which I get to the most senior bit 6 only signals, finding schies in the lower subband, and a buffer

cascade 9 - upper subband signals. Consequently, in the analog storage device 8, only stresses smaller than the reference voltage 11, i.e., are stored. smaller than, / ujf ../ Kg /. Therefore, the error, due to dielectric absorption, is significantly reduced. This eliminates the effect of dielectric absorption. At the same time, the basics. The comparative 3 produces samy. the high bit for the signals in the upper subband, and the comparator 9 refines the performance of the

the higher bit for the signals in the lower subband, which eliminates the possibility of overlapping scales.

The conversion time consists of the memorization time in the analog storage device 8 .. -, y, the time of establishment of the amplifier 7 of the time of the transition process in the comparator - with

the recording time in

fOAin

trigger memory of bit 10 of the oldest bit 9.- ", and the time of memorization in the analog memory

l

device 8) -

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V F F, V i F. V V. F V V

С / сг сгсз у, у, yt У iff 12 3

Claims (1)

MULTI-DISCHARGE LOGARITHMIC, CUE ANALOG-DIGITAL CONVERTER containing a synchronization unit, a buffer cascade, a main comparator, two voltage reference sources and discharge shapers, each of which contains a series-connected amplifier and an analog storage device, the comparator whose output is connected to the information input a memory trigger, the output of which is connected to the input of the gain control of the amplifier and the information input of the shift register, the first input of the comparator is connected to the output of the first reference voltage source, the control input of the analog storage device is connected to the reset input of the memory trigger and one output of the synchronization unit, the buffer cascade contains serially connected buffer amplifier and buffer analog storage device, the control input of which is connected to the control input of the analog storage device of the first having formed a discharge body, the first input of the main comparator is connected to the output of the second reference voltage source, different t we note that, in order to simplify, an input key is inserted into each discharge driver, the output of which is connected to the output of the analog storage device and the input of the amplifier, the output of the latter is connected to the second input of the comparator and the input of the input key of the subsequent discharge driver, two keys are introduced into the buffer cascade of the converter , the output of the first of them is connected to the output of the buffer analog storage device and the input of the buffer amplifier, the output of which, through another key, is connected to the input of the amplifier of the second driver s to defuse, the input transducer is connected to the input of the input key of the first form ⁴ · rovatelya discharge input of the first klyuchb buffer stage and the second input of the stop novnogo comparator connected access to the trigger input sync block, the other outputs sync block are connected to respective control inputs of the input keys of the first and second shapers of the discharge and the control input of the second key of the buffer stage, the outputs of the digital registers are the bit outputs of the converter. I