JPH06125228A - Offset voltage correction circuit - Google Patents

Abstract

PURPOSE:To provide an offset voltage correction circuit which can decrease the number of additional external parts with no control required and also is not required to increase the transistor size. CONSTITUTION:The non-inverted input terminal of an input buffer amplifier 12 of a sequential comparison type A/D converter is grounded. Then the output voltage of a comparator 14 is stored in an offset storing capacitor 17 when the amplifier 12 and its subsequent comparator 14 are actuated as the voltage followers. Then the voltage of the capacitor 17 is impressed to a part between the non-inverted input terminal and the output terminal of the amplifier 12 as the offset voltage when the amplifier 12 and the comparator 14 are normally actuated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset voltage correction circuit for collectively correcting offset voltages of a plurality of operational amplifiers.

[0002]

2. Description of the Related Art For example, a successive approximation type A / D converter takes in an analog voltage with a sample and hold circuit and outputs it as an output voltage (a digital value once obtained is compared with an analog voltage for comparison). (Converted into voltage) is compared with a comparator and converted into a digital value. At the time of this comparison, the comparison reference value is sequentially changed to change the MSB.
The bit value of each digit from (the most significant digit) to LSB (the least significant digit) is obtained.

However, since an offset voltage is generated in the operational amplifier used in the sample and hold circuit and the operational amplifier used in the comparator, this appears as an error.

Therefore, in order to suppress this offset voltage, conventionally, as shown in FIG. 6, the digital value "0" is output when the analog voltage 0v is input.
For example, an input terminal 3 is provided separately from the input terminal 2 to which the sample and hold voltage of the comparator 1 is input, and an offset correction voltage is applied to the input terminal 3. 4 is a D that converts the output digital value into an analog value as a comparison value
/ A converter, 5 is an output terminal.

As another method, the transistor of the error amplifier in the operational amplifier is shaped so that the offset voltage is reduced (the gate length of the transistor is lengthened or the shape of the transistor is devised) when laying out the IC chip. Etc. were adopted.

[0006]

However, in the method of applying the bias voltage by the offset voltage to the input terminal as described above, the number of external parts is increased and external adjustment is required. Mass productivity is poor. Also, I
In the method of devising the shape of the transistor at the time of chip layout when the C layout is adopted, there are problems that the area of the transistor is increased and the entire chip area is increased, or the variation of the offset voltage is increased.

An object of the present invention is to provide an offset voltage correction circuit which solves the above-mentioned problems by requiring a small number of external parts, requiring no adjustment and increasing the size of the transistor.

[0008]

Therefore, according to the present invention, in a circuit in which a plurality of operational amplifiers are connected in cascade, when the input terminals of the operational amplifiers at the front stage are grounded and all the operational amplifiers function as voltage followers. The output voltage of the final stage operational amplifier is stored in the offset voltage storage capacitors, and when the above-mentioned all operational amplifiers are normally operated, the voltage of the capacitors is offset to the input side of the frontmost operational amplifier. It was configured to be applied as a voltage.

[0009]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of an embodiment applied to a successive approximation A / D converter. Reference numeral 11 is an input terminal to which an analog voltage is applied, 12 is an input buffer amplifier including an operational amplifier for amplifying the analog voltage, 13 is a holding capacitor, and 15 is a D / which converts a previously obtained digital value to an analog value. An A converter, 14 is a comparator composed of an operational amplifier for comparing the output voltage of the D / A converter 15 and the voltage of the capacitor 13, and 16 is an output terminal. Further, 17 is a capacitor for accumulating offset voltage, S1 to
S10 is a switch.

This circuit detects the falset voltage of the entire system prior to the original operation. At this time, as shown in FIG. 1, the switches S1, S5, S8 and S9 are turned off and the remaining switches S2 to S4, S6, S7 and S10 are turned on. As a result, the amplifier 12 has an output terminal and an inverting input terminal connected to each other and functions as a voltage follower, and the voltage applied to the non-inverting input terminal is 0 v. Therefore, although the voltage of the capacitor 13 is originally 0v, if the amplifier 12 has an offset, the offset voltage is charged. Further, since the comparator 14 at the next stage also acts as a voltage follower, the voltage of the capacitor 13 is output as it is. However, if there is an offset, the voltage obtained by adding the voltage of the capacitor 13 and the offset voltage is output. Then
This charges the capacitor 17. In this way
The capacitor 17 is charged with a voltage obtained by adding the offset voltages of both the amplifier 12 and the comparator 14.

Next, a sample operation is performed. At this time,
As shown in FIG. 2, switches S1, S4, S5, S8,
S9 is turned on and the remaining switches S2, S3, S6, S
7. Turn off S10. As a result, the analog voltage applied to the input terminal 11 is applied to the non-inverting input terminal of the amplifier 12, and the offset voltage component accumulated in the capacitor 17 is generated between the inverting input terminal and the output terminal of the amplifier 12. Apply between. Therefore, the offset voltage component is added to the input analog voltage as a canceling voltage, and the offset component generated in the amplifier 12 is canceled here. Also, this capacitor 13
Since the voltage charged in the comparator 14 is a voltage including the offset voltage cell voltage of the comparator 14, a voltage in which the offset component generated therein is canceled is obtained at the output terminal of the comparator 14. In this way, the output terminal 16
A voltage obtained by canceling both the offset voltage of the amplifier 12 and the offset voltage of the comparator 14 is obtained.

Here, the offset voltage component is fed to the amplifier 1
Although it is connected between the inverting input terminal and the output terminal without being applied between the inverting input terminal and the ground, the offset voltage component can be canceled without depending on the input analog voltage.

Next, at the time of holding, as shown in FIG. 3, the switch S4 on the input side of the capacitor 13 is turned off. In this state, the output voltage of the D / A converter 15 and the analog input voltage can be compared without the offset voltage until the completion of the successive approximation operation.

FIG. 4 is a diagram showing the voltage characteristics of the above operation. The voltage on the non-ground side of the capacitor 17 is Va, the voltage on the non-inverting input terminal of the amplifier 12 is Vb, and the voltage on the inverting input terminal of the amplifier 12 is. Where Vc is Vc and the voltage on the non-grounded side of the holding capacitor 13 is Vd, the respective voltage changes are shown. Vin is an analog input voltage applied to the input terminal 11, Vo1 is an offset voltage of the amplifier 12, Vo2
Is the offset voltage of the comparator 14. Also, time t1
The switch-switching state of FIG. 1 was previously used, the switch-switching state of FIG. 2 is performed after time t2, and the transition period is from t1 to t2.

FIG. 5 is a diagram showing another embodiment, in which a holding capacitor 13 is connected between the non-inverting input terminal of the amplifier 12 and the switch S1. In this circuit, the amplifier 12 is held after the input analog voltage is held.
The operation is the same as that of the above-mentioned embodiment except that the input is made to.

The above embodiment is applied to the successive approximation type A / D converter.
Considering the hold capability of the above, it is preferable to perform the offset cancel operation every time the comparison operation is performed. The offset voltage correction circuit is not limited to the successive approximation A / D converter described above, but can be similarly applied to a circuit in which a plurality of operational amplifiers (not limited to two) are cascade-connected.

[0017]

As described above, according to the present invention, only one capacitor for accumulating the offset voltage component is required as the external component, no adjustment is required, and it is not necessary to increase the size of the transistor. It is possible to stably reduce the offset voltage component without increasing the chip area. Further, it becomes possible to cancel the offset component of each of the plurality of operational amplifiers of the circuit in which the plurality of operational amplifiers are connected in series, and it is possible to expect a great effect when applied to various circuits. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sample hold unit and a comparison unit of a successive approximation A / D converter to which an offset voltage correction circuit according to an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram of a sample hold unit and a comparison unit of the converter for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram of a sample hold unit and a comparison unit of the converter for explaining the operation of the embodiment.

FIG. 4 is a voltage characteristic diagram for explaining the operation of the embodiment.

FIG. 5 is a circuit diagram of a sample hold unit and a comparison unit of a successive approximation A / D converter to which an offset voltage correction circuit according to another embodiment is applied.

FIG. 6 is a circuit diagram of an input unit and a comparison unit of a successive approximation type A / D converter to which a conventional offset voltage correction circuit is applied.

[Explanation of symbols]

11: input terminal, 12: amplifier for input buffer, 13:
Hold capacitor, 14: comparator, 15: D / A
Converter, 16: output terminal, 17: capacitor for offset voltage storage.

Claims (1)

[Claims] 1. In a circuit in which a plurality of operational amplifiers are connected in cascade, the output voltage of the final operational amplifier when the input terminal of the operational amplifier at the frontmost stage is grounded and all operational amplifiers are operated as a voltage follower. An offset characterized by being stored in a capacitor for storing an offset voltage and applying the voltage of the capacitor as a canceling voltage to the input side of the operational amplifier at the frontmost stage when all the operational amplifiers described above are normally operated. Voltage correction circuit.