SU1149313A1 - Storage with detection of most probable errors - Google Patents

Abstract

1. A MEMORIZE DEVICE WITH DETECTION OF THE MOST PROBABLE ERRORS, containing a parity signal generator, a comparison unit and a accumulator, the numerical inputs of which are the information inputs of the device and connected to one of the inputs of the first parity signal generator, the output of which is connected to the first control input of the circuit pack, which contains the pattern for the input of the first parity signal generator, the output of which is connected to the first control input from the inputs of the comparison unit are connected respectively to the first control output of the accumulator and to the output of the second generator of the parity signals, one of the inputs of which is under Connected to the numerical outputs are the accumulator, the output of the comparison unit and the numerical outputs of the accumulator are, respectively, the control and information outputs of the device, characterized in that, in order to improve the accuracy of the control, the third and fourth parity signal generators, convolution blocks and elements of the elements And, one of the inputs of the first convolution block is connected to the digital inputs of the accumulator, the numerical outputs of which are connected to one of the inputs of the second convolution block, the outputs of the first convolution block are connected to with the first and second inputs of one of the elements of the first group, and the outputs of the second convolution unit g, respectively, with the first and second inputs of one of the elements of the second group, the outputs of the elements of the first group are connected to the inputs of the third generator of the parity signals, the output of which is connected to the second control input of the accumulator, the outputs of the elements And the second group are connected to the inputs of the fourth generator of the parity signals, the output of which and 4ib the second control output of the accumulator are connected to the other inputs of the unit cf Avneni. oo

Description

2. The device according to claim 1, characterized in that the third inputs of one of the elements of the first and second groups are connected respectively to the numerical inputs and to the numerical outputs of the storage device.

3. The device according to claim 1, characterized in that the third and fourth convolution blocks are entered into it, one of the inputs of which are connected respectively to the numerical inputs and the digital outputs of the accumulator, and the outputs are connected to the third inputs of one of the elements of the first and second groups respectively.

4. Device on PP. 1 and 3, characterized in that the fourth inputs of one of the elements of the first and second groups are connected respectively to numerical inputs and to numerical outputs of a storage ring.

5. Device on PP. 1 and 3, characterized in that the first and second groups of OR elements are entered into it, one of the inputs of which are connected respectively to the numerical inputs and to the digital outputs of the accumulator, and the fourth inputs of one of the elements AND of the first group are connected respectively to the outputs of the elements OR of the first group and with the outputs of the third convolution unit, and the fourth outputs of the AND elements of the second group, respectively, with the outputs of the OR elements of the second group and with the outputs of the fourth convolution unit.

6. The device according to claim 1, characterized in that the address inputs of the accumulator are connected to other inputs of the first and second parity signal generators, the first and second convolution units.

7. The device according to paragraphs. 1, 2 and 6, characterized in that the address inputs of the accumulator are connected to the inputs of other elements AND of the first and second groups.

8. Device on PP. 1, 3 and 6, characterized in that the address inputs of the accumulator are connected to other inputs of the third and fourth convolution units.

9. The device according to paragraphs. 1, 4 and 8, characterized in that the address inputs of the storage device are connected to the inputs of other elements of the first and second groups.

10. Device on PP. 1, 5 and 8, characterized in that the address inputs of the storage device are connected to other inputs of the OR elements of the first and second groups.

one

The invention relates to computing, in particular, to storage devices running on integrated circuits.

A device with the detection of the most probable errors is known, which contains a modular drive and means of detecting errors based on a modification of the Hamming code 1.

The disadvantage of this device is the low accuracy of the control.

The closest to the invention is a memory device with detection of the most probable errors, containing a drive, parity signal generators, read amplifiers whose inputs are connected to the drive outputs, and the outputs to the information register inputs, address decryptors, address keys and comparison unit, one from the inputs of which is connected to the control outputs of the information register 2.

A disadvantage of the known device is the low accuracy of the control, since it does not detect faults of even multiplicity and does not control the address chains.

The purpose of the invention is to improve the accuracy of control, as well as to ensure the possibility of detecting address errors and using memory modules with a number of bits from five to eight.

The goal is achieved by the fact that in a memory device with the detection of the most probable errors, containing parity signal generators, a block

comparison and storage, the numerical inputs of which are informational inputs of the device and connected to one of the inputs of the first generator of parity signals, the output of which is connected to the first control input of the storage device, and one of the inputs of the comparison unit is connected respectively to the first control output of the storage device and to the output of the second driver parity signals, one of the inputs of which is connected to the numerical outputs of the accumulator, the output of the comparison unit and the numerical outputs of the accumulator are respectively The third and fourth parity signal generators, convolution blocks, and groups of elements And,

0 and one of the inputs of the first convolution unit is connected to the digital inputs of the accumulator, the numerical outputs of which are connected to one of the inputs of the second convolution unit, the outputs of the first convolution unit are connected

respectively, with the first and second inputs of one of the elements of the first group, and the outputs of the second convolution unit, respectively, with the first and second inputs of one of the elements of the second group, the outputs of the elements of the first group are connected to the inputs of the third shaper of the parity signals, the output of which is connected to the second the control input of the accumulator, the outputs of the elements And the second group are connected to the inputs of the fourth generator of the parity signals, the output of which and the second control output of the accumulator are connected to other inputs of the unit cf Avneni.

The third inputs of one of the elements And the first and second groups are connected respectively to the numerical inputs and to the numerical outputs of the drive.

At the same time, the device includes the third and fourth convolution blocks, one of the inputs of which are connected respectively to the numerical inputs and to the digital outputs of the accumulator, and the outputs are connected to the third inputs of one of the And elements of the first and second groups, respectively.

The fourth inputs of one of the elements of the first and second groups are connected respectively to the numerical inputs and to the numerical outputs of the drive.

In addition, the first and second groups of elements OR are entered into the device, one of the inputs of which are connected respectively to the numerical inputs and to the digital outputs of the accumulator, the fourth inputs of one of the elements AND of the first group are connected respectively to the outputs of the elements OR of the first group and with the outputs of the third block convolutions, and the fourth outputs of elements AND of the second group - respectively with the outputs of the elements OR of the second group and with the outputs of the fourth convolution unit.

The address inputs of the accumulator are connected to other inputs of the first and second parity signal drivers of the first and second convolution blocks.

Address inputs of the drive are connected to the inputs of other elements And the first and second groups.

The address inputs of the accumulator are connected to other inputs of the third and fourth convolution blocks.

Address inputs of the drive are connected to the inputs of other elements And the first and second groups.

The address inputs of the accumulator are connected to other inputs of the elements OR of the first and second groups.

FIG. I shows a functional diagram of the device in the first embodiment; in fig. 2-5 - the same, other embodiments; in fig. 6 is a functional diagram of the most preferred embodiment of the first (second) convolution unit and its connection with elements AND of the first (second) group for the first embodiment; in fig. 7-10 - the most preferred options for combining elements AND the first

(second) groups for other embodiments of the device.

The proposed device in the first and second versions of its implementation comprises g (Figs. 1 and 2) drive 1, made on memory modules 2, with address 3, control 4 and 5 and numeric 6 inputs, first convolution unit 7, first driver 8 parity signals, the first group of elements And 9, shapers 10-12 signals

 the second to fourth parities, the second convolution unit 13, the comparison unit 14 and the second group of elements 15.

FIG. 1-5 are the numerical outputs 16, the control inputs 17 and the outputs 18

5 storage device and control output 19 of the device.

In the first embodiment of the device, the drive 1 is made on four-bit memory modules 2, and in the second version - on five-bit memory modules 2

0 memory. In the third, fourth and fifth embodiments of the device, the drive 1 is made on six-, seven-, and eight-bit memory modules 2, respectively.

5 In the third and fourth embodiments, the device also contains (FIGS. 3 and 4) the third 20 and fourth 21 convolution blocks.

In the fifth embodiment, the device also contains (FIG. 5) the first 22 and the second 23 groups of OR elements.

Drive 1 consists of M modules 2 memories with a number of bits K (where K has a value from four to eight). Accordingly, the inputs 6 and 3 and the outputs 16 of accumulator 1 are distributed into M groups by

5 to the bits in each group, which are connected to the inputs of the respective groups of elements in blocks 7, 13, 20, and 21 of convolution, elements AND 9 and 15, and accements OR 22 and 23 in accordance with FIG. 1 -10.

0 FIG. 6 shows a part of a convolution unit 7, to the outputs of which direct 6i-64 and inverse 6i-64 values of one four-bit group of inputs 6 are fed.

The part of block 7 of convolution contains the UNEQUALITY elements 24 and 25 and the elements AND 26-29. Blocks 7 and 13 consist of similar parts, the number of which is equal to the number of groups of inputs 6 and 3 (or inputs 3 and outputs 16) connected to the inputs of blocks 7 (or 13).

0 FIG. 6 also shows the elements

And 9t-9s, at the outputs 30-34 of which the values of the second check bit for one four-bit group of inputs 6i-64 are formed. FIG. 6 indicated the outputs 35-40 of the block 7 and the inputs 41-46

5 elements and.

FIG. Figures 7-10 show the elements AND 9 (15) used to process the values received respectively according to n TI-, six-, seven-, and eight-bit group of inputs 6 (or outputs 16) and 3. FIG. 8-10 denotes the group of outputs 47-59 of block 20 and the group of outputs 60; and 61 elements And 22, direct 65, 6 and inverse 65, 6 7 values respectively of the fifth and seventh bits of the inputs 6. The group of elements And 15 is similar to the group of elements And 9. The inputs of the elements OR 20 and 21 are inverse values of bits from the fifth to the eighth in each eight-bit group of inputs 6, inputs 3 and outputs 16, respectively. The device works as follows. The operation of the device will be considered on the example of the formation of a control code for four-bit memory modules 2 (Fig. 1). in the recording mode, the inputs of the drive 1 receive the codes of addresses of the numbers to be recorded in the next cycle. Input 4 sets the recording resolution potential, and inputs 6 receive numbers codes that should be written to this address. The codes of the numbers also go to the shaper 8, where the total parity is determined, and to the inputs of block 7. The table shows the principle of the formation of check bits. 1. In the first column of the table. Table 1 lists all possible combinations of code values at the inputs of four-bit memory modules 2. They are divided into five groups according to the number of units in a group of four bits. This is done because with unidirectional failures, the transition code combinations to each other with the same number of units is impossible and, therefore, they may have the same control code. This control code is presented in the second column. The third column presents the code that is obtained after determining the total parity, and the fourth column presents the correction codes (the second check digit) to be obtained at the output of the driver. In the fifth and ninth columns of the table. Figure 1 shows the values of A, B. C, D, D corrections obtained with the aid of And 9, -9s elements (Fig. 6). In tab. 2 Karno presents all the combinations that require their encoding in this case. A minimized mathematical expression is presented that allows one to obtain the value of the P corrections for one four-bit group. Pr. (Xi @ Xg) (XsF X,), @ 9Xa). (Xi X) XiXj Sh.H. ffi.XjXA, where the .X, -X4 values of the code bits at the outputs 6, inputs 3 or the outputs 16. The values of the corrections obtained for all M groups enter the shaper 10, where the final value of the second check bit is determined. The obtained values of the check bits are fed to the inputs 17 of the accumulator 1. After the application of the inversion signal on the input 5, the information values of the number code are recorded from the inputs 6, and the control codes on the inputs 17 to the accumulator 1. Formation of the value of the second check digit with the values K from five to eight similar to that described, with the only exception that a larger number of elements participate in its formation, in accordance with FIG. 2-5 and FIG. 6-10. As can be seen from the table. 2, there are only two combinations that can go one into the other and that have the same control code. These codes are 0000 and 1111. Therefore, an error in this case will not be detected. However, the percentage of errors detected is 93.7. In read mode, the operation of the device is similar. The inputs 3 receive the address codes, the input 4 the read resolution potential, and the input 5 the access signal. At outputs 16 and 18, the values of the read codes of the information and check bits, respectively, appear. The generation of control signals for readings occurs in block 13, elements I 15, driver 10 and 12, similarly to that described during recording. The values of the check bits received at the outputs of the formers 10 and 12 and read from the outputs 18 are fed to the inputs of block 14, where they are compared, and this way the error is detected when the codes in block 14 do not match. If drive 1 is organized from modules 2 with different bit sizes , for example, four and eight, it is possible to provide different degrees of protection for the most significant (four-bit modules 2) and younger (eight-bit) digits of the number code from failures. The number of modules 2 of that and the other size is determined from the requirements for the reliability of storage and reading of information. Since a greater percentage of error detection is provided in four-bit modules 2, this allows for improved reliability of information storage. The technical and economic advantage of the device proposed is a higher accuracy of control compared to the known one.

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Claims (10)

1. A MEMORY DEVICE WITH DETECTION OF MOST PROBABLE ERRORS, containing parity signal generators, a comparison unit and a drive, the digital inputs of which are information inputs of the device and connected to one of the inputs of the first parity signal generator, the output of which is connected to the first control input of the drive the inputs of the comparison unit are connected respectively to the first control output of the drive and to the output of the second driver of the parity signals, one of whose inputs s to the numerical outputs of the drive, the output of the comparison unit and the numerical outputs of the drive are respectively the control and information outputs of the device, characterized in that, in order to increase the accuracy of the control, the third and fourth shapers of parity signals, convolution blocks and groups of elements And are introduced into it, one of the inputs of the first convolution unit is connected to the numerical inputs of the drive, the numerical outputs of which are connected to one of the inputs of the second convolution unit, the outputs of the first convolution unit are connected respectively the first and second inputs of one of the elements AND of the first group, and the outputs of the second block § convolution - respectively, with the first and second inputs of one of the elements AND of the second I / group, the outputs of the elements AND of the first group I *] are connected to the inputs of the third formation - | (parity signal carrier, the output of which is connected to the second control input of the drive S, the outputs of the And elements of the second group are connected to the inputs of the fourth driver of the parity signals, the output of which and the second control output of the drive are connected to other inputs of the unit tions. FIG. / 2. The device according to π. 1, characterized in that the third inputs of one of the elements And the first and second groups are connected respectively to the digital inputs and to the digital outputs of the drive. 3. The device according to π. 1, characterized in that the third and fourth convolution blocks are introduced into it, one of the inputs of which are connected respectively to the digital inputs and to the digital outputs of the drive, and the outputs are connected to the third inputs of one of the And elements of the first and second groups, respectively. 4. The device according to paragraphs. 1 and 3, characterized in that the fourth inputs of one of the elements And the first and second groups are connected respectively to the digital inputs and the digital outputs of the drive. 5. The device according to paragraphs. 1 and 3, characterized in that the first and second groups of OR elements are introduced into it, one of the inputs of which are connected respectively to the numerical inputs and to the numerical outputs of the drive, and the fourth inputs of one of the elements of the first group are connected respectively to the outputs of the elements OR περ howl groups and with the outputs of the third convolution block, and the fourth outputs of the AND elements of the second group, respectively, with the outputs of the OR elements of the second group and with the outputs of the fourth convolution block. 6. The device according to π. 1, characterized in that the address inputs of the drive are connected to other inputs of the first and second drivers of the parity signals, the first and second convolution blocks. 7. The device according to paragraphs. 1, 2 and 6, characterized in that the address inputs of the drive are connected to the inputs of other elements And the first and second groups. 8. The device according to paragraphs. 1, 3 and 6, characterized in that the address inputs of the drive are connected to other inputs of the third and fourth convolution blocks. 9. The device according to paragraphs. 1, 4 and 8, characterized in that the address inputs of the drive are connected to the inputs of other elements And the first and second groups. 10. The device according to paragraphs. 1, 5 and 8, characterized in that the address inputs of the drive are connected to other inputs of the OR elements of the first and second groups. ί