SU1149316A1 - Storage - Google Patents

Abstract

1. A STORAGE DEVICE containing a drive, the numerical inputs of which are connected to one of the inputs of the parity signal generators of the first group, the outputs of which are connected to the inputs of the first parity signal generator, the output of which is connected to the first control input of the accumulator, whose numerical outputs are connected to one of the inputs of the formers parity signals of the second group, the outputs of which are connected to the inputs of the second generator of the parity signals, and the comparison unit one of the inputs of which are connected respectively one of the control outputs of the accumulator and the output of the second parity signal generator, and the output of the comparison unit is the control output of the device, the information inputs and outputs of which are numerical inputs and outputs of the accumulator, in order to improve the accuracy of control of the device the third and fourth formers of parity signals, a group of elements NOT, a group of elements OR — NOT, a group of elements OR, and a group of elements AND from the first to the sixth, and one of the inputs of the elements IL The first group and elements of the first group are connected to the digital inputs of the accumulator, one of the inputs of the elements OR of the second group and the elements of the second group are connected to the digital outputs of the accumulator, the inputs of the elements of the first group and the inputs of the first group of elements AND of the third group are connected to the outputs of the parity drivers the first group, the outputs of the elements OR of the first group are connected to the inputs of the first group of elements OR NOT the first group and the inputs of the second group of elements AND the third group, the outputs of the elements AND the first group with united with the inputs of the first group of elements And the fifth group, the outputs of the elements NOT the first group, the elements OR NOT the first group and the elements of the third and fifth groups are connected to the inputs of the third parity signal generator, the output of which is connected to the second control input of the accumulator, the outputs of the parity signal shapers of the second group are connected to the inputs of the NOT elements of the second group and the inputs of the first group of elements AND the fourth group whose inputs of the second group and the inputs of the first group of elements OR NOT of the second group are connected The outputs of the elements OR of the second group, the outputs of the elements AND of the second group are connected to the inputs of the first group of elements AND the sixth group, other inputs of the unit compared to SG) are connected respectively to the second control output of the accumulator and to the output of the fourth parity signal generator, whose inputs are connected to the outputs elements of the second group, elements OR of the second group, elements of the fourth and sixth groups. 2. The device according to claim 1, characterized in that the inputs of the third group of elements of the third and fourth groups are connected respectively to the outputs of the elements of the first group and to the outputs of elements of the second group and the inputs of the second group of elements of the fifth and sixth groups are connected respectively to the outputs of the elements OR first

Description

groups and to the outputs of the elements OR of the second group.

3. The device according to PP. 1 and 2, characterized in that the inputs of the second group of elements OR — NO of the first group, the inputs of the third group of elements AND of the fifth group and the inputs of the fourth group of elements AND of the third group are connected to the numerical inputs of the accumulator, and the inputs of the second group of elements OR — NOT the second group , the inputs of the third group of elements And the sixth group and the inputs of the fourth group of elements And the fourth group are connected to the numerical outputs of the drive.

4. Device on PP. 1 and 2, characterized in that the address inputs of the accumulator are connected to other inputs of the parity drivers of the first and second groups, the elements of the first and second groups, and the elements of the first and second groups.

5. Device on PP. 1 3 and 4, characterized in that the address inputs of the accumulator are connected to the inputs of the fifth group of elements AND the third and fourth groups, the inputs of the fourth group of elements AND the fifth and sixth groups and the inputs of the third group of elements OR-NOT the first and second groups.

one

The invention relates to computing and can be used in the development of storage devices made on integrated circuits.

A device containing a modular drive and error detection tools based on a modification of the Hamming code I is known.

The disadvantages of this device are the inability to detect three-bit errors and hardware complexity.

Closest to the invention is a memory device containing a drive, the address inputs and outputs of which are connected to the outputs and inputs of keys, the other inputs of which are connected to the outputs of the decoders, the parity signal generators, the read amplifiers, the outputs of which are connected 2

A disadvantage of the known device is low control accuracy, since it does not detect all errors of even multiplicity in four-bit memory modules, control of address circuits is not available, and control is not provided when using five to eight memory modules.

The purpose of the invention is to improve the control accuracy by detecting the most probable errors, as well as ensuring the possibility of detecting address errors and using memory modules with the number of bits from five to eight.

The goal is achieved by the fact that in a memory device containing a drive, the numerical inputs of which are connected to one of the inputs of the parity signal generators of the first group.

the outputs of which are connected to the inputs of the first generator of parity signals, the output of which is connected to the first control input of the accumulator, the numerical outputs of which are connected to one of the inputs of the drivers of parity signals of the second group, the outputs of which are connected to the inputs of the second generator of parity signals, and the comparison unit, one of the inputs which are connected respectively to

one of the control outputs of the accumulator and the output of the second generator of the parity signals, and the output of the comparison unit is the control output of the device, information inputs and outputs of which are numerical inputs and outputs of the accumulator, the third and fourth signal formers, parity, groups of elements NOT , groups of elements OR-NOT, groups of elements OR, and groups of elements AND from the first to the sixth, and one of

0 inputs of elements OR of the first group and elements AND of the first group are connected to numerical inputs of the accumulator, one of the inputs of elements, OR of the second group and elements AND of the second group are connected to

the digital outputs of the accumulator, the inputs of the NOT elements of the first group and the inputs of the first group of elements AND the third group are connected to the outputs of the parity drivers of the first group, the outputs of the elements OR of the first group are connected to

0 inputs of the first group of elements OR NOT the first group and inputs of the second group of elements AND the third group, the outputs of the elements AND the first group are connected to the inputs of the first group of elements AND the fifth group, the outputs of the elements NOT the first group, the elements OR NOT the first group and the elements AND the third and fifth groups are connected to

the inputs of the third signal generator, parity, the output of which is connected to the second control input of the accumulator, the outputs of the parity signal generators and the second group are connected to the inputs of the NOT elements of the second group and the inputs of the first group of elements AND the fourth group, the inputs of the second group and the inputs of the first group of elements OR- NOT of the second group are connected to the outputs of the elements OR of the second group, the outputs of the elements of the second group are connected to the inputs of the first group of elements AND the sixth group, the other inputs of the comparison unit are connected to Corresponding to the second control output of the accumulator and to the output of the fourth generator of the parity signals, the inputs of which are connected to the outputs of the NOT elements of the second group, the OR elements of the second group, the elements of the fourth and sixth

groups.

In this case, the inputs of the third group of elements AND of the third and fourth groups are connected respectively to the outputs of elements AND of the first group and to the outputs of elements AND of the second group, and the inputs of the second group of elements AND the fifth and sixth groups are connected respectively to the outputs of the elements OR of the first group and to the outputs of elements OR of the second group.

In addition, the inputs of the second group of elements OR are NOT the first group, the inputs of the third group of elements AND of the fifth group and the inputs of the fourth group of elements AND of the third group are connected to the numerical inputs of the accumulator, and the inputs of the second group of elements OR NOT of the second group, the inputs of the third group of elements And the sixth group and the inputs of the fourth group of elements And the fourth group are connected to the numerical outputs of the drive.

The address inputs of the accumulator are connected to other inputs of the parity signal generators of the first and second groups, the elements of the first and second groups, and the elements of the first and second groups.

The address inputs of the accumulator are connected to the inputs of the fifth group of elements AND of the third and fourth groups, the inputs of the fourth group of elements And the fifth and sixth groups and the inputs of the third group of elements ORINE of the first and second groups.

FIG. shows the functional diagram of the proposed device for the main variant of its implementation; in fig. 2-8 are functional diagrams of the device for other embodiments thereof.

In the main embodiment, the proposed device (Fig. 1) comprises a storage device 1, made on four-bit memory modules 2, c. address 3, control 4, 5 and numeric 6 inputs, the first group of generators 7 parity signals, the first group of elements OR 8, the first group of elements AND 9, the first generator 10 of parity signals, the first group of elements NOT 11, the group of elements And 12 -16 from second to sixth. Drive 1 has numeric outputs 17.

The device also contains the second group of parity signal generator 18, the second group of elements OR 19, the comparison unit 20, the second generator of parity signal 21, the second group of elements HE 22, the first 23 and second 24 groups of elements OR NOT, the third 25 and fourth 26 drivers. parity signals. This marked the first control inputs 27 and the output 28 of the drive 1, the control output 29 of the device and the second control input 30 of the drive 1.

In the second embodiment of the device (Fig. 2), the drive 1 can be made on six- or eight-bit memory modules 2, and in the third variant (Fig. 3) - on five or seven-bit memory modules 2. Drive 1 consists of M modules 2 memories, each of blocks 7–9, 11–16, 18, 19, 22–24 consists of a similar number of corresponding elements. This means that each K-bit of the bottom is a group of inputs 3, 6 and outputs 17 (where K is 1,2 3, 4) is fed to the inputs of the corresponding of the formers 7 and 18, elements OR 8 and 19, elements 9, 12-16 and elements OR NOT 23 and 24.

FIG. 4-8 show the connections between one of the formers 7, one of the AND 9, 13, and 15 elements, the OR 8 elements, the NOT 11 elements, and the OR-NOT 23 elements for examples of connecting one group of inputs (or inputs 3i-3g), sh. of four - eight bits, respectively. Connections between driver 18 are similar; the elements OR 19, the elements AND 12, 14 and 16, the elements NOT 22 and the elements OR NOT 24 for connecting the group of outputs 12.

The device works in the following way.

The operation of the device will be considered for an example of four-bit modules 2 (Fig. 1).

In the recording mode, inputs 3 receive the address codes of the numbers to be recorded in the next write cycle. Input 4 sets the recording resolution potential, and inputs 6 receive numbers codes that should be written to this address. Each K-bit group of inputs 3, 6 and outputs 17 is processed independently of the other groups of inputs 3, 6 and outputs 17, and then the values of the control bits from each group are fed to the formers 10 and 25 (during recording), which determine the values the control bits for all M groups of inputs 3 and b, which are written into the control bits of accumulator 1. The process of generating the values of the control bits is divided into three stages. At the first stage, one of the formers 7, two of the elements OR 8 and two of the elements AND 9 for each of the groups of inputs (for example, 6) work, as a result a parity sign is produced, as well as pairwise conjunctions and disjunctions, i.e. zero and single pairs of bits. At the second stage, one of the elements is NOT 11, the element OR-NOT 23, the elements AND 13 and 15, which allows to determine a completely zero code, a completely single code and a code containing three units in a four-bit group of inputs 6. After the second stage, the control the code for each four-bit group of inputs 6 is separately prepared, and the final code for the entire word, consisting of M groups of inputs 6, is obtained at the third stage in generators 10 and 25, the outputs of which form the values of two test bits, which after signaling appeal the course 5 is recorded in the control bits of accumulator 1 to the inputs 27 and 30 and to the inputs of six values recorded information bits. One bit (right in the table) is the total parity signal of the whole word, to which is added the value of the second check bit, generated using the parity signal, conjunction and disjunction of the individual bits. As a result, codes of numbers having a different number of ones have a different control code (exception: the code of the number "O is equal to the code of the number" is four, i.e. a failure in the form of a combination transition 0000 to combination 1111 and is not detected back), and the transition codes having the same number of units, each other is impossible with unidirectional failures. The formation of check bits at K from five to eight is similar to that described, however, a larger number of logical elements participate in the formation of the second check bit. The values of the control bits for the address inputs 3 are formed in the same way. In the read mode, inputs 3 receive address codes, input 4 gives the read resolution signal, and input 5 receives the access signal. The control code values are generated from the values of the read information in the same way as described in the recording mode with the formers 18, 21, and 26, the elements of OR 19, the elements of AND 12, 14, and 16, and the elements OR NOT 24. In block 20, the values of the control bits are compared The drives coming from the outputs of the formers 21 and 26, with the values of the bits of the same name, read from accumulator 1 through the outputs 28. In the absence of an error in the read information, output 29 appears a coincidence signal, in the presence of a fault, a mismatch signal. The table shows the control code values for four to eight-bit memory modules 2, respectively. Digit B of the first column indicates the number of units in the K group of inputs 3, 6 or outputs 17 under consideration. Thus, codes having the same number of units in the K group of groups are assembled into one line and they are assigned the same control code. The second column indicates the values of the control code (two bits) after calculating the parity, i.e., at the outputs of the formers 7 and the HE 11 elements (for writing) or at the outputs of the formers 18 and the HE elements for 22 (for reading). The third column shows the values of the control codes at the outputs of drivers 10 and 25 (when writing) or 21 and 26 (when reading). If drive 1 is organized from modules 2 of different sizes, for example, four and eight bits, then it is possible to provide different degrees of protection for older (four-bit modules) and younger (eight-bit) bits of the number code from failures. The number of modules of the one and the other size is determined from the requirement for the reliability of storage and reading of information. Since in four-bit modules 2 the detection of a greater number of errors is provided, this makes it possible to increase the reliability of information storage. The technical and economic advantage of the proposed device is a higher accuracy of the control, compared with the known device, when using only two test bits in the drives.

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Claims (5)

1. A MEMORY DEVICE containing a drive, the numerical inputs of which are connected to one of the inputs of the first signal shaper of the first group, the outputs of which are connected to the inputs of the first shaper of the parity, the output of which is connected to the first control input of the drive, the numerical outputs of which are connected to one of the shapers parity signals of the second group, the outputs of which are connected to the inputs of the second driver of the parity signals, and the comparison unit ^ one of the inputs of which are connected respectively to one of the control outputs of the drive and the output of the second driver of the parity signals, and the output of the comparison unit is the control output of the device, the information inputs and outputs of which are the digital inputs and outputs of the drive, characterized in that, in order to improve the accuracy of control of the device, the third and fourth shapers of parity signals, groups of elements NOT, groups of elements OR NOT, groups of elements OR and groups of elements I through VI, one of the inputs of OR elements of the first group s and elements of the first group are connected to the digital inputs of the drive, one of the inputs of the OR elements of the second group and the elements of the second group are connected to the digital outputs of the drive, the inputs of the elements are NOT the first group and the inputs of the first group of elements of the third group are connected to the outputs of the parity drivers the first group, the outputs of the OR elements of the first group are connected to the inputs of the first group of elements OR NOT the first group and the inputs of the second group of elements AND the third group, the outputs of the elements AND of the first group are connected to the inputs the first group of elements AND the fifth group, the outputs of the elements NOT of the first group, the elements OR NOT the first group and the elements of the third and fifth groups are connected to the inputs of the third driver of the parity signals, the output of which is connected to the second control input of the drive, the outputs of the drivers of the parity signals the second group are connected to the inputs of the NOT elements of the second group and the inputs of the first group of AND elements of the fourth group, the inputs of the second group of which and the inputs of the first group of OR elements of the second group are connected to the outputs of the OR elements in of the second group, the outputs of the AND elements of the second group are connected to the inputs of the first group of the AND elements of the sixth group, the other inputs of the comparison unit are connected respectively to the second control output of the drive and to the output of the fourth driver of the parity signals, the inputs of which are connected to the outputs of the NOT elements of the second group, the elements OR NOT the second group, elements of the fourth and sixth groups. 2. The device according to π. 1, characterized in that the inputs of the third group of AND elements of the third and fourth groups are connected respectively to the outputs of the AND elements of the first group and to the outputs of the AND elements of the second group, and the inputs of the second group of AND elements of the fifth and sixth groups are connected respectively to the outputs of the OR elements of the first group and to the outputs of the elements OR of the second group. 3. The device according to paragraphs. 1 and 2, characterized in that the inputs of the second group of OR-HE elements of the first group, the inputs of the third group of AND elements of the fifth group and the inputs of the fourth group of AND elements of the third group are connected to the digital inputs of the drive, and the inputs of the second group of OR-HE elements of the second group, the inputs of the third group of elements And the sixth group and the inputs of the fourth group of elements And the fourth group are connected to the numerical outputs of the drive. 4. The device according to paragraphs. 1 and 2, characterized in that the address inputs of the drive are connected to other inputs of the shapers of the parity signals of the first and second groups, OR elements of the first and second groups and elements AND of the first and second groups. 5. The device according to paragraphs. 1 3 and 4, characterized in that the address inputs of the drive are connected to the inputs of the fifth group of elements AND of the third and fourth groups, the inputs of the fourth group of elements Й of the fifth and sixth groups and the inputs of the third group of elements OR NOT the first and second groups.