SU1136171A1 - Device for checking completeness of program testing - Google Patents

Abstract

A DEVICE FOR CHECKING THE COMPLETENESS OF TESTING PROGRAMS containing a memory block whose address and control read inputs are respectively an information input and a device check start input, the information output of the memory block is a device check output, characterized in that, in order to increase the completeness of control , an adder and a delay element are entered into it, and the start-up check input of the device is connected via a delay element to the control input of the memory block, the information output of the memory block oedinen to the input of the first adder operand, the second operand input being connected to the input of a single device capacity, output of the adder is connected to the data input of the memory unit. oh :) oh)

Description

The invention relates to digital computing and can be used to verify the completeness of testing programs of specialized control digital computers that have a read-only memory (ROM) for program placement, and also allow the possibility of connecting, instead of the ROM, an external adjustment memory block. A device for tracing programs is known, which contains a memory block (stack) that is connected to a backbone of a digital computer, logical nodes, and display circuits. After launching the program under study in a digital computer, the logical nodes ensure that the stack is sequentially filled with the addresses of executable jump instructions, and after filling the last address, a record is organized from the starting address. When the program is stopped, the display device makes it possible to display the contents of stack 1. However, this device is focused on debugging programs and can give a limited assessment of the completeness of testing, since it contains a stack for storing the final sequence of command addresses of only one type (transition) and does not allow completeness evaluation testing according to known criteria for assessing the quality of the test. The closest in technical essence to the present invention is a device for checking the completeness of testing programs, which consists of a single-bit memory block and a control logic block. The one-bit memory block operates in parallel with the memory adjustment block of the specialized digital computer. When the program under study starts in the digital computer, the logical node ensures that the digital computer fails when accessing the addresses of the memory block into which units 2 are pre-recorded. However, the known device only allows to evaluate the quality of testing the protection system of the program being investigated from hardware-detected failures and It provides an opportunity to systematically evaluate the quality of testing according to known criteria. The aim of the invention is to increase the completeness of testing programs according to a systematic criterion, based on fixing the actual operation of all references of the studied DVM program to commands and operands. The goal is achieved by the fact that the device for checking the completeness of testing programs, which contains a memory block, the address and control read inputs of which are respectively informational in-line and a device checkup start input, the information output of the memory unit is a device checkout output an adder and a delay element are entered, the input of the device test start through the delay element is connected to the recording control input of the memory block, the information output of the memory block is connected to the input of the first the accumulator peranda, the input of the second operand of which is connected to the input of the unit potential of the device, the output of the adder is connected to the information input of the memory unit. FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 is a diagram of the operation of the device; where € m is the circulation period of the digital computer () to the ROM, Bees is the read cycle in the memory unit, s, is the sum setting time at the output of the adder, Cj is the delay time of the signal in the delay element, bpz is the write cycle in the memory unit, Sy - the cycle of the device. A device for checking the completeness of testing programs contains a memory block 1, a delay element 2, and an adder 3. The address inputs and control read inputs of memory block 1 are connected to the corresponding outputs of a digital computer 4 in parallel with a ROM 5 (or a setup memory block) containing the program. The first input of the adder 3 is connected to the output information outputs of the memory block 1 to the second input of the adder 3 is constantly fed to one, and the output of the adder 3 is connected to the input of the first memory block 1. The output of delay element 2 is connected to the input of the “Record of memory block 1”. The second input of memory block I is connected to the instrumental digital computer 6, which is used to prepare the device for operation and to process the results obtained by the device. The device works as follows. Previously, in block 1 of the memory, all the cells were nullified with the aid of an instrumental digital computer 6. Next, a program under test is lowered to digital computer 4. Since the device is connected to the address line and the control line Reading Digital Computer 4 in parallel with ROM 5, simultaneously with addressing Digital Computer 4 to a certain address, a command or operand reads information from the same memory block 1 to the same address. The number read from memory block 1 is fed to the first input of adder 3, where one is added to it, continuously supplied by the circuit input to the second input of adder 3. The resulting number is written to memory block 1 at the same address by the signal write generated from the read signal delayed by the value of delay element 2. Thus, each cell

, memory block 1 works as a counter of the number of calls to it. The memory block 1 size corresponds to the maximum allowed number of calls to any command (operand) for testing programs. The volume of the memory block 1 is equal to the volume of the ROM 5 -CBM 4.

Under such conditions, the device provides a count of the number of calls to each command (operand) when testing programs. The obtained distribution of calls to all commands and operands of the programs is transmitted to the instrumental digital computer 6 for processing and makes it possible to objectively assess the quality and completeness of testing by the number of calls / to all addresses. In particular, in the absence of calls to some addresses of ROM 5 (zeros in the corresponding cells of memory block 1) test

the program does not meet the coverage criteria of all operators. The device also makes it possible to purposefully form a sequence of tests to ensure the quality and completeness of testing.

Experiments show that for programs operating on a real-time basis, tests selected on the basis of a functional feature do not cover about 1.5% of the volume of the program under study.

The proposed device makes it possible to attain SOA / about the coverage of the program with a test, which makes it possible to detect at the preliminary stage 70% of the errors that were previously detected only at the stage of operating the programs. In addition, the device also makes it possible to reduce the amount of testing programs by a factor of 2-3 by removing the highly intersecting tests.

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Output Information

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Adder Record

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Claims (1)

DEVICE FOR CHECKING THE COMPLETENESS OF TESTING PROGRAMS, containing a memory block, the address and control reading inputs of which are respectively the information input and input of the device test start, the information output of the memory block is the device test output, characterized in that, in order to increase the completeness of control, they are introduced into it an adder and a delay element, and the input of the device check start through the delay element is connected to the control input of the memory block record, the information output of the memory block is connected ene to the input of the first adder operand, second operand input connected to the input of a single device capacity, output of the adder is connected to the data input of the memory block. 5S £ Fig