JPH1186595A - Semiconductor memory test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory test device in which hardware can be simply constituted and which has an inexpensive defect relieving and analyzing device without using a conventional defective analyzing memory in which fail information for each cell of a semiconductor memory to be tested is held. SOLUTION: This test device is provided with a defect relieving and analyzing device having a row fail numbers storing memory 3 storing directly the number of fail for each row address of a semiconductor memory to be tested and a column fail numbers storing memory 4 storing directly the number of fail for each column address, and a fail address memory 81 storing an address at the time of fail of a semiconductor memory to be tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test apparatus, and more particularly, to a semiconductor memory test apparatus having a failure repair analysis apparatus for a semiconductor memory having a redundancy structure.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of a failure analysis of a semiconductor memory under test by a semiconductor test device having a failure repair analysis device.
A very general description is provided with reference to FIG. The pattern generator 2 operates according to the reference clock generated by the timing generator 1, and generates an address signal, test pattern data, and a control signal. These signal data are supplied to the waveform shaper 3, where they are shaped and input to the semiconductor memory M under test. Here, the semiconductor memory under test M
The test data is written to the memory cell specified by the waveform-shaped address signal. Next, the logical value output from the semiconductor memory M under test is read out, and the read logical value is compared with expected value data generated and supplied from the pattern generator 2 in the logical comparator 4 to determine whether the read / write operation is good or not. Is determined. If the logical value read from the semiconductor memory M under test does not match the expected value data generated and supplied from the pattern generator 2, fail data is output and is input to the defect relief analyzer 5.

[0003] Here, a defect in the semiconductor memory is caused by one of the memory cells connected to the decoder due to a defect in the decoder or the like.
Line defects in which a large number of memory cells fail in a row or one column can be roughly classified into cell failures in which defective memory cells are dispersed independently. A semiconductor memory having a redundancy structure includes a structure in which, when a defective memory cell is present, a spare memory cell to be replaced with the defective memory cell and an address of the defective memory cell is converted to an address of the spare memory cell. Refers to a semiconductor memory having The spare memory cell is called a spare line because it is replaced in row or column line units. Defective repair means that when a defect occurs in the original memory cell of the semiconductor memory under test, the address of the defective memory cell is searched, and the defective memory cell is replaced with a spare line to make the semiconductor memory under test a non-defective product. It refers to checking whether it can be used, and if it can be used, analyzing which spare line in a row or a column should be replaced.

Next, an algorithm of failure repair analysis by the failure repair analyzer will be described with reference to FIG. In order to perform the defect repair analysis of the semiconductor memory under test M by the defect repair analyzer, it is necessary to know the number of failures on each address line of the memory cell row and column. 2 spare rows
There are four spare rows. The spare row is a row side spare line, and the spare column is a column side spare line. Here, if it is assumed that five failures indicated by x have occurred on the row address RA1, and when the repair is to be performed by using the spare column, only four spare columns are prepared, so that one is insufficient. However, depending on the spare row, five fail cannot be relieved. Therefore, row address line RA1 is repaired by a spare row. In other words, a line defect is a memory defect that can be remedied only by one spare line.

Referring to FIG. 5, a column address line CA
If it is assumed that three failures have occurred on 1, the number of spare rows is two and cannot be repaired by the spare rows. Therefore, the column address line CA1
Are relieved by spare rows. As described above, repair of a defect that cannot be repaired by one spare line but can be repaired by the other spare line is performed first. This remedy is mainly performed for a line defect. The remedy for the remaining failures after performing the line defect remedy, that is, the cell defect is performed.
In this case, the repair can be performed by using either the spare row or the spare column. In this case, all possible combinations of rescue are obtained, or conditions are set to obtain an optimal remedy solution. For example, the condition for using up from the spare row is set and the relief is performed.

Incidentally, the conventional failure repair analysis device performs a failure analysis using a failure analysis memory, and the failure repair analysis device can be roughly classified into the following two types.
The first type of defect repair analysis apparatus has a memory for storing the number of failures for each row address and column address in addition to the failure analysis memory, and counts the number of failures during the test of the semiconductor memory under test. is there. When a fail is stored at a certain address in the failure analysis memory, if the data at that address is "0", counting is performed, and if "1", counting is not performed. This is a function necessary for performing a read operation several times for the same address in a normal memory test and counting a failure generated at the same address as one time.

The first type of defect repair analysis device will be described in detail with reference to FIG. The row failure number storage memory 3 is a memory for storing the number of failures on the line for each row address, and the column failure number storage memory 4 is a memory for storing the number of failures on the line for each column address. The row fail number adder 31 and the column fail number adder 41 are adders that count up the fail number when a failure occurs. The first AND gate 11 is a gate for writing data into the failure analysis memory m only when a failure occurs. The second AND gate 21 is a gate that writes data to the row failure number storage memory 3 and the column failure number storage memory 4 only when the data in the failure analysis memory m is “0”. Here, the write enable signal WE1 is applied later than the write enable signal WE2.

A second type of defect repair analysis apparatus temporarily stores a test result of a semiconductor memory under test in a defect analysis memory, and after completion of the test, reads the defect information stored in the defect analysis memory to read out each row and column. Is counted. The count value is stored in the main memory of the CPU and is used for defect repair analysis.

[0009]

In the above-described first type of defect repair analysis apparatus, it is not necessary to read the entire area of the defect analysis memory after the test of the semiconductor memory under test is completed. Two are required, which leads to an increase in the cost of the defect repair analysis device.

The second type of defect analysis apparatus has the advantage that no special hardware other than the defect analysis memory is required, but has the disadvantage that it takes a long time to read data from the defect analysis memory. Have. This becomes more remarkable as the memory capacity of the semiconductor memory under test increases. Further, all of the above defect repair analysis devices require a defect analysis memory. In this case, when the memory capacity of the semiconductor memory under test increases, it becomes necessary to prepare a failure analysis memory having a correspondingly large memory capacity, which also increases the cost of the failure repair analysis apparatus.

An object of the present invention is to provide a semiconductor memory test apparatus having an inexpensive defect repair analysis apparatus in which the above-mentioned problems are solved by simply configuring hardware.

[0012]

[Means for Solving the Problems]

Claim 1: Failure repair analysis having a row fail number storage memory for directly storing the number of failures for each row address of the semiconductor memory under test M and a column failure number storage memory for directly storing the number of failures for each column address In a semiconductor memory test apparatus provided with a device, a semiconductor memory under test M
The semiconductor memory test apparatus provided with the fail address memory 81 for storing the address at the time of the failure.

In the semiconductor memory test apparatus according to the present invention, a row address is selected from the addresses supplied from the pattern generator and supplied to the row fail number storage memory. An address selector 5 and a column address selector 6 for selecting a column address and supplying the same to the column failure number storage memory are provided.
The row fail number adder 31 for outputting the added result of 1 and the column fail number adder 4 for outputting the added result of adding +1 to the column fail number read from the column fail number storage memory 4
1, a row limit value register 32 for storing the limit value of the number of row failures, and a column limit value register 42 for storing the limit value of the number of column failures. The output of the row failure number adder 31 and the row limit value A row fail number comparator 33 comparing the row limit value of the register 32 and a column fail number comparator 43 comparing the output of the column fail number adder 41 with the column limit value of the column limit value register 42.
The write enable terminal WE of the row failure number storage memory 3 and the column failure number storage memory 4 is connected to a failure signal input terminal, and the output terminal of the row failure number adder 31 and the output of the row failure number comparator 33 are provided. A terminal is connected to the input terminal Di of the row failure number storage memory 3, and an output terminal of the column failure number adder 41 and an output terminal of the column failure number comparator 43 are connected to an input terminal Di of the column failure number storage memory 4. An AND gate 82 for connecting the non-inverting input terminal to the input terminal of the fail signal and connecting the inverting input terminal to the output terminal of the row fail number comparator 33 and the output terminal of the column fail number comparator 43; And an address adder 83 for inputting and adding the output of the address adder. A semiconductor memory test apparatus is provided with a fail address memory 81 having an address input terminal A to which the output of the device 83 is input and a write enable terminal WE to which the output of the AND gate 82 is input.

In a preferred embodiment of the present invention, the limit value of the number of failures is set to (the number of spare columns) × (the number of times of reading one address). Was configured.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. Note that the circuit on the column side can be similarly described in comparison with the circuit on the row side, and thus the description thereof is omitted. In FIG. 1 and FIG.
Is a selector for selecting a row address of the semiconductor memory under test M from address signals supplied from the pattern generator.

The row failure number storage memory 3 is a memory for storing the number of failures for each row address. The row fail number storage memory 3 outputs read data to the row fail number adder 31 every time a fail signal is input through the input AND gate 7 serving as an input terminal, and also outputs the row fail number adder. The operation of writing the output data of the row fail number comparator 31 and the output data of the row fail number comparator 33 is executed. The row fail number storage memory 3 has a data width of (m + 1) bits, and has an address range equal to or greater than the row address range of the semiconductor memory M under test. The address range m is determined by the number of failures in one row. The +1 bit is a bit for writing a flag, which is output data of the row fail number comparator 33.

The row fail number adder 31 outputs data obtained by adding +1 to the read data input from the row fail number storage memory 3. The adder 31 reads out the current data in the memory 3 regardless of whether or not data has been written to the row-fail count storage memory 3, adds "1" to this data, and feeds back the addition result to the memory 3. I do. The operations of the row fail number storage memory 3 and the row fail number adder 31 will be specifically described later.

The row fail number limit value register 32 stores
This register stores the limit value of the row fail. Although specific numerical values will be described later with reference to FIG. 2, “(the number of spare columns) × (the number of times of reading one address)” is set here. This corresponds to detecting a line defect that can be repaired only by one spare line in the description of the conventional example. In the present invention, since the failure information for each bit of the semiconductor memory M to be tested cannot be held, if the same address fails twice, the failure is counted as 2. Therefore, (the number of spare rows) × (the number of times of reading one address) is set as the limit value.

The number-of-row-fails comparator 33 stores the output of the row-fail-number adder 31 and the row-fail-number limit value register 3.
If the output of the row fail number adder 31 is larger than the limit value of 2, the output is "1" and the flag 1 is set, otherwise "0" is output. . here,
81 is a fail address memory. A row address and a column address are supplied as input data to an input terminal Di of the fail address memory 81 via a row address selector 5 and a column address selector 6. The write enable terminal WE of the fail address memory 81 is supplied with the output of the row fail number comparator 33 or the output of the column fail number comparator 43 and a fail signal input via the input AND gate 7 via the AND gate 82. Is done. The output of the AND gate 82 is supplied to the address input terminal A of the fail address memory 81 via the address adder 83 as an address signal. In addition,
“0” is applied to the address input terminal A of the address adder 83 in the cleared initial state. That is,
It is in a state where address 0 can be specified.

The operation of the defect repair analyzer of FIG. 1 will be described with reference to FIG.
Is an example having 8 rows × 8 columns of memory cells. Hereinafter, a row address is indicated by i, a column address is indicated by j, and this address is indicated by an address (i, j). The data reading of the semiconductor memory under test M is 1 for one address.
The number of spare rows is four, and the number of spare columns is also four. That is, the row fail number limit value register 3
2 is set to (4 × 1) = 4, and (2 × 2) = 4 is also set to the column fail number limit value register 42.

First, the fail number storage memory, the fail address memory, and the address adder are cleared before starting the test. Start the test for the 0 row address. When the address (0, 0) of the semiconductor memory M under test is specified, the test result is a pass, so that the failure is “0”,
Since the fail input of the input AND gate 7 is "0",
The output of the input AND gate 7 is "0". Therefore, the row fail number storage memory 3 is not write enabled since the input of the input terminal WE is "0". next,
The row fail number adder 31 reads out the cleared data “0” from the row fail number storage memory 3 and inputs it. The row fail number adder 31 adds "1" to the read data "0", and feeds back the added result "1" to the row fail number storage memory 3 as input data. However, as described above, since the row failure number storage memory 3 is not write enabled, the input data "
1 "is not stored. Therefore, the row failure number storage memory 3
The number of failures, which is the stored content of "1", remains at "0".

Next, when the address (0, 1) is designated, the failure is "0", so that the storage content of the row failure number storage memory 3 is "0" as in the case of the address (0, 0). "It doesn't change. Subsequently, the address (0,
2) Even when addresses (0, 7) are sequentially specified,
Since the fail input is "0", the content stored in the row fail number storage memory 3 remains "0".

The test of one row address is started. When the address (1, 0) is specified, the test result is a failure. In the case of a failure, the input AND in FIG.
The gate 7 outputs “1” to the write enable terminal WE of the row failure number storage memory 3, and outputs the row failure number storage memory 3.
Is write enabled. At this time, the output read from the row fail number storage memory 3 by the row fail number adder 31 is "0", and "1" is a result of adding "1" to this.
As input data to the row-fail-number storage memory 3 and fed back. Here, since the row-fail count storage memory 3 is write-enabled, the input data that has been fed back and supplied "
Therefore, the number of failures stored in the row failure number storage memory 3 is rewritten from "0" to "1".

Here, as described above, the output "0" which is the cleared initial state of the address adder 83 is applied to the address input terminal A of the fail address memory 81. The result obtained by adding “1” to the output read from the row fail number storage memory 3 by the row fail number adder 31 is also supplied to the fail number comparator 33. That is, the addition result “1” of the row fail number adder 31 is also supplied to the fail number comparator 33 and compared with the row fail number limit value “4”. Since the comparison result is A <B,
The fail number comparator 33 does not raise the flag “1” and outputs 0, which is supplied to the inverting input terminal of the AND gate 82 via the OR gate 84 to make the AND gate 82 conductive. Therefore, the fail signal “1” of the address (1, 0) is supplied to the write enable terminal WE of the fail address memory 81 via the AND gate 82, and the write enable of the fail address memory 81 is enabled. As a result, the address 0 applied to the address input terminal A of the fail address memory 81 is write-enabled, and the address (1, 0) designated here is written.
Is stored as a fail address. At this time, the fail signal "1" of the address (1, 0) is added to the address adder 83.
And the count value is set to "1". Here, the count value “1” is applied to the address input terminal A of the fail address memory 81.

When the address (1, 1) is designated, the test result is "fail", so the fail is "1". That is,
Subsequently, since a failure occurs, the storage content of the row failure number storage memory 3 is rewritten. The output read from the row failure number storage memory 3 by the row failure number adder 31 is “1”, and “2”, which is the result of adding “1” thereto, is fed back to the row failure number storage memory 3 as input data. The "2" is supplied to the row failure number storage memory 3 as the number of failures. As a result, the storage content of the row failure number storage memory 3 is rewritten from "1" to "2". On the other hand, regarding the fail address memory 81, an address adder 83 is connected to its address input terminal A.
Output "1" is applied. The result of adding “1” to the output “1” read out from the row failure number storage memory 3 by the row failure number adder 31 is the same as the failure number comparator 3
3, and the result of addition "2" is compared with the row fail number limit value "4". The comparison result is A <B,
The fail number comparator 33 does not raise the flag “1” and outputs 0, which is supplied to the inverting input terminal of the AND gate 82 via the OR gate 84 to make the AND gate 82 conductive. Therefore, the fail signal of the address (1, 1) is supplied to the write enable terminal WE of the fail address memory 81 via the AND gate 82, and the write enable of the fail address memory 81 is enabled. As a result, the address 1 applied to the address input terminal A of the fail address memory 81 is write-enabled, and the designated address (1, 1) is stored as a fail address. At this time, the fail signal of the address (1, 1) is also supplied to the address adder 83, and the count value is set to "2". Here, this count value “2” is applied to the address input terminal A of the fail address memory 81, and the address 2 can be designated.

When the address (1, 2) is designated, the test result is "1", so the row failure number storage memory 3
Is rewritten. The output read from the row failure number storage memory 3 by the row failure number adder 31 is “2”, and “3” which is the result of adding “1” to this is stored in the row failure number storage memory 3 as the number of failures. Is done. On the other hand, regarding the fail address memory 81, the output “2” of the address adder 83 is applied to the address input terminal A thereof. By the way, the result of adding "1" to the output "2" read out from the row fail number storage memory 3 by the row fail number adder 31 is also supplied to the fail number comparator 33, and the added result "3" is output to the line This is compared with the fail number limit value “4”. The comparison result is A <B, and the fail number comparator 33 outputs 0 without setting the flag “1”, which is supplied to the inverting input terminal of the AND gate 82 via the OR gate 84, and Gate 82
Are in a conductive state. Accordingly, the fail signal of the address (1, 2) is supplied to the write enable terminal WE of the fail address memory 81 via the AND gate 82, and the write enable of the fail address memory 81 is enabled. As a result, the address 2 applied to the address input terminal A of the fail address memory 81 is write-enabled, and the designated address (1, 2) is stored as a fail address. At this time, the fail signal of the address (1, 2) is also supplied to the address adder 83, and the count value is set to "3". Here, this count value “3” is applied to the address input terminal A of the fail address memory 81, and the address 3 can be designated.

When the address (1, 3) is designated, the test result is "1", so the row failure number storage memory 3
Is rewritten, and the number of failures is "4".
Is stored in the row failure number storage memory 3. The addition result “4” of the row failure number adder 31 is compared with the row failure number limit value “4”. Since the comparison result is not A> B, the flag “1” is not set and 0 is output. Gate 82
Are in a conductive state. Therefore, the fail signal at the address (1, 3) enables the fail address memory 81 to be write-enabled. As a result, the fail address memory 8
Address 3 applied to the address input terminal A of No. 1 is write-enabled, and the specified address (1,
3) is stored as a fail address. For the fail signal of the address (1, 3), the count value of the address adder 83 is set to "4". This count value “4” is applied to the address input terminal A of the fail address memory 81, and the address 4
Can be specified.

The address (1, 4) is designated. Since the test result is failure "1", the storage contents of the row failure number storage memory 3 are rewritten, and "5" is stored in the row failure number storage memory 3 as the number of failures. Here, “5” which is the addition result of the row fail number adder 31 is compared with the row fail number limit value “4” in the fail number comparator 33. The comparison result is A> B, and the fail number comparator 3
3 sets a flag "1". This is OR gate 84
Is supplied to the inverting input terminal of the AND gate 82 via
The AND gate 82 is turned off. Therefore, the fail signal of the address (1, 4) is not supplied to the write enable terminal WE of the fail address memory 81 via the AND gate 82, and the fail address memory 81 is not write enabled. As a result, the address (1, 4) designated as address 4 applied to the address input terminal A of the fail address memory 81 is not stored as a fail address. And the AND gate 82
Is in a non-conducting state, the fail signal of the address (1, 4) is not supplied to the address adder 83, and the count value is kept at "4". That is, the count value “4” is still applied to the address input terminal A of the fail address memory 81, so that the address 4 can be designated.

When the address (1, 5) is designated, the test result is "1", so the row fail number storage memory 3
Is rewritten, and the number of failures is "6".
Is stored in the row failure number storage memory 3. However, since the comparison result in the fail number comparator 33 is A> B, the address 4 is not write enabled as in the case where the address (1, 4) is designated. No fail address is stored in the fail address memory 81. The count value “4” is still applied to the address input terminal A of the fail address memory 81, so that the address 4 can be designated.

When the address (1, 6) is designated, the test result is "1", so that the row failure number storage memory 3
Is rewritten, and the number of failures is "7".
Is stored in the row failure number storage memory 3. However, since the comparison result in the fail number comparator 33 is A> B, the address 4 is not write enabled. No fail address is stored in the fail address memory 81. The count value "4" is stored in the fail address memory 8
1 is still applied to the address input terminal A, so that the address 4 can be designated.

When the address (1, 7) is designated, the test result is "1", so the row failure number storage memory 3
Is rewritten, and the number of failures is "8".
Is stored in the row failure number storage memory 3. However, since the comparison result in the fail number comparator 33 is A> B, the address 4 is not write enabled. No fail address is stored in the fail address memory 81. The count value "4" is stored in the fail address memory 8
1 is still applied to the address input terminal A, so that the address 4 can be designated.

The test of the two-row address is started. Just as in the case of the test for the 0-row address, rewriting of the storage contents of the row-fail count storage memory 3 and storage of the fail address in the fail address memory 81 are not performed. The count value "4" is stored in the fail address memory 81.
Is kept applied to the address input terminal A, so that the address 4 can be designated.

The test of the three row addresses is started. When the address (3, 2) is designated, since the test result is "1", the storage contents of the row failure number storage memory 3 are rewritten, and "1" is stored in the row failure number storage memory 3 as the number of failures. Is stored. Row fail number adder 3
The addition result “1” of “1” is compared with the row fail number limit value “4”. Since the comparison result is not A> B, the flag “1” is not set and “0” is output, and the AND gate 82 is turned on. I have to. Therefore, the fail signal at the address (3, 2) enables the fail address memory 81 to be write-enabled. As a result, the address 4 applied to the address input terminal A of the fail address memory 81 is write-enabled, and the designated address (3, 2) is stored as a fail address. For the fail signal of the address (3, 2), the count value of the address adder 83 is set to “5”.
This count value "5" is applied to the address input terminal A of the fail address memory 81, and the state where the address 5 can be designated is established.

Thereafter, the fail address is stored in the fail address memory 81 at the addresses (5, 5) and (5, 6).

[0035]

As described above, according to the present invention, the conventional failure analysis memory for holding the fail information for each cell of the semiconductor memory under test is not used.
Instead, a row failure number storage memory for storing the number of failures for each row address of the semiconductor memory under test and a column failure number storage memory for storing the number of failures for each column address are used, but these memory capacities are extremely small. It is small and it is not necessary to increase the memory capacity according to the memory capacity of the semiconductor memory under test. Accordingly, the hardware can be simply configured, and a semiconductor memory test device having an inexpensive defect repair analysis device can be provided.
The limit value of the number of failures is (number of spare rows) x
By setting (the number of times of reading one address), it is possible to easily determine a line defect, and to efficiently perform a defect repair analysis.

Further, after the test is completed, the row address and the column address of the line failure can be recognized by reading the flag bits of the row failure number storage memory and the column failure number storage memory. Then, by removing the line defective address from the data stored in the fail address memory, the cell defective address can be known. Therefore, when performing a defect repair analysis of a semiconductor memory, it is possible to efficiently obtain address information to be repaired.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment.

FIG. 2 is a diagram illustrating the operation of the embodiment.

FIG. 3 is a diagram illustrating a conventional example of failure analysis.

FIG. 4 is a view for explaining an algorithm of defect repair analysis.

FIG. 5 is a view for explaining an algorithm of defect repair analysis.

FIG. 6 is a diagram illustrating a conventional example of a defect repair analysis device.

[Explanation of symbols]

 3 Row fail count storage memory 31 Row fail count adder 32 Row fail count limit register 33 Row fail count comparator 4 Column fail count storage memory 41 Column fail count adder 42 Column fail count limit register 43 Column fail count comparator 5 row address selector 6 column address selector 7 input AND gate 81 fail address memory 82 address input AND gate 83 address adder 84 OR gate A address input terminal Di input terminal M semiconductor memory under test WE write enable terminal

Claims (3)

[Claims] 1. A defect remedy analysis device having a row failure number storage memory for directly storing the number of failures for each row address of a semiconductor memory under test and a column failure number storage memory for directly storing the number of failures for each column address. A semiconductor memory test apparatus comprising: a fail address memory for storing an address of a semiconductor memory under test when a failure occurs. 2. The semiconductor memory test apparatus according to claim 1, wherein a row address is selected from addresses supplied from a pattern generator and supplied to a row fail number storage memory. A row fail number adder for selecting an address and supplying the selected address to the column fail number storage memory, outputting a result of adding +1 to the row fail number read from the row fail number storage memory, and a column fail number A row limit value register for storing a limit value of the number of row failures and a column limit for storing a limit value of the number of column failures are provided with a column fail number adder for outputting an addition result obtained by adding +1 to the number of column failures read from the storage memory. It has a value register, the output of the row fail number adder and the row limit value of the row limit value register A column fail number comparator for comparing the output of the row fail number comparator and the column fail number adder to be compared with the column limit value of the column limit value register is provided, and the write enable of the row fail number storage memory and the column fail number storage memory is provided. The terminal is connected to the input terminal of the fail signal, the output terminal of the row fail number adder and the output terminal of the row fail number comparator are connected to the input terminal of the row fail number storage memory, and the output terminal of the column fail number adder and The output terminal of the column fail number comparator is connected to the input terminal of the column fail number storage memory, the non-inverting input terminal is connected to the fail signal input terminal, and the inverting input terminal is the output terminal of the row fail number comparator and the column fail. An address adder connected to an output terminal of the number comparator and having an output of the AND gate input and added; And Bei, an input terminal to which the row and column addresses are inputted,
A semiconductor memory test apparatus comprising: a fail address memory having an address input terminal to which an output of an address adder is input and a write enable terminal to which an output of an AND gate is input. 3. The semiconductor memory test apparatus according to claim 2, wherein the limit value of the number of failures is (the number of spare rows) × (1
(The number of times of reading addresses).