SU1128294A1 - Storage with error correction - Google Patents

Abstract

The ERROR FIXED DEVICE, containing the address register, multiplexer, comparison unit, accumulator, number register, logic unit, control unit and control unit, the output of the address register is connected to the first inputs of the comparison unit and multiplexer, and the input is the device address input the multiplex output is connected to the first input of the accumulator, the first output of which is connected to the first input of the number register, the second input of which is connected to the first output of the logic block, the first input of the logic block, the input, the control unit and the output of the number register are the information output of the device, the information input of which is the second input of the logic unit, the first one. The output of the control unit is connected to the third inputs of the register: the number and the logic unit and the second input of the accumulator, the second output and the first input of the control unit are respectively controlling the output and input of the device, the second and third INPUTS are connected to the outputs of the comparison unit and the control unit respectively , characterized in that, with a chain of increasing the reliability of the device, additional drives, a control information register, a buffer register and a modified address register, whose input is connected, are entered into it to the first output of the control unit, and 5 the output is connected to the second inputs of the comparison unit and the multiplexer, the output of which is connected to the first inputs of additional drives, one of the inputs of the control information register is connected respectively to the outputs of additional drives and the second output of the logic unit, and the outputs to the second inputs of the additional E X solid drives and the third input of the logic unit, the first output of the control unit 1C is connected to the third inputs of the additional drives and the multiplexer, the other input control unit peiPHCTra and one of the inputs of the buffer register, the other inputs of which are connected respectively to the second input of the register of numbers and the information input of the device, and the output is connected to the third input of the storage device.

Description

The invention relates to computing, in particular, to storage devices. A self-monitoring memory device is known that contains a storage group, a decoder, a control unit and a control unit, with the drive outputs connected to the input of the control unit GL. The disadvantages of this device are the limited possibility of its use and the inability to correct erroneous information. The closest to the invention is a memory device containing a drive, a control unit, an arithmetic unit, an error detection and correction unit, a first, second and third registers, the input of the detection and correction unit being connected to the input of the device, the first output - with the first input of the third register, the second output with the input of the control unit and the first input of the arithmetic unit, the second input of which is connected to the first output of the control unit, the third input - to the output of the third register, the first output - to the input of the first the register, the output of which is connected and the first output of device 2. A disadvantage of the known devices is the low reliability of communication with the necessity of correcting the same error each time it is addressed along an adress containing an error. . , -; The purpose of the invention is to increase the reliability of the device. The goal is achieved in that an error correction device containing an address register, a multiplexer, a comparison bypass, a drive, a perHctp logic block, a control block and a control unit, the output of the address register is connected to the first input of the comparison block and a multiplexer The input is the address input of the device, the output of the multiplexer is connected to the first drive input, the first output of which is under: 5kkmen to the first input of the number register, the second input of which is connected to the first output of the logic unit, The first input of the logic unit, the input of the control unit and the output of the register are the information output of the device, the information input of which is the second input of the logic unit, the first output of the control unit is connected to the third inputs of the number register and the logical unit and the second input of the accumulator, the second output and the first input of the control unit are respectively the control output and the input of the device; the second and the third inputs are connected to the outputs of the control unit, respectively; additional accumulators are entered, register the control information, the buffer register and the modified address register, whose input is connected to the first output of the control unit, and the output is connected to the second inputs of the comparison unit and the multiplexer, the output of which is connected to the first inputs of the additional data storage devices, respectively you move additional drives and the second output of the logic unit; and the outputs - to the second inputs of additional drives and the third input of the Logic block, the first LED of the output; the block is connected to the third inputs of additional drives and the multiplexer, another input of the control information register and one of the inputs of the buffer register, the other inputs of which are connected respectively by the second input The number of registers and information input device: and the output is connected to the third input of the drive. Figure 1 shows a block diagram of the proposed device / on, figure 2 - time diagrams of his work ...,. . - .J., / Memorizing device with correction, errors contains the address register t having input 2, comparison block 3, multiplexer 4, drive 5, re-; Gistr 6 numbers. Logic block 7, while it has information output 8 and input 9, as well as control block 10 having input 11 and output 12, control block 13, modified address register 14, additional drives 15 and 16, respectively, used to store horizontal and vertical control szgmm, buffer register 17. and register 18 control information

The control unit 10 may be made of a series-connected address address generation unit, microinstructions, microinstructions register and a decoder.

The device works as follows.

The address arriving at the input 2 of register 1 is stored therein and then through the multiplexer 4, controlled by the control unit 10, arrives at the input of the accumulator 5. Simultaneously, at the input 11 of the unit 10, the Record or Read signal enters the control unit 10, which organizes the operation of the device respectively in the mode of writing or reading (figure 2).

In Reading mode, drive 5 enters the register 6 word read at the received address. From the output of the register 6, the information is fed to the input of block 13. The latter analyzes the health of the information and, through the control block-10, in the case of good information, allows entry of the sign of issuing information on its code 12.

Thus, with good information, the speed of the memory device does not decrease and is equal to the nominal speed of the accumulator 5 (FIG. 2, mode. Reading).

In recording mode, the device accepts information in the register .17 and then operates autonomously. The control unit 10 on the incoming signal Organizes the initial reading of information from accumulator 5. At the same time, accumulators 15 and 16 read out the checksums of the memory area to which they were accessed, and through register 18 they enter the input of unit 7. Under control of unit 10, block 7 KoppekTHpyeT value of checksums, subtracting the value of the read information (contents of register 6) and cz the world value of the content of peTHCTpia 17. The corrected control sums are placed back into register 18. Thereafter, the control In block 10, information from register 17 and checksums from register 1 are recorded in drive 5 and drive 15 and 16, respectively.

Thus, the controls are modified by recording each

The new knowledge of the information and always reflect the actual contents of the accumulator 5 (figure 2, Record mode)

If an error is detected by block 13, it is prohibited to remove information from the device from the indication of the information. With one error word, control block 10 organizes reads. the horizontal checksum of the memory area in which an error is detected produces a sequential reading of the entire memory area and subtracting the checksum value by means of block 7. A deliberately erroneous word, which is determined by comparison of addresses by comparison unit 3, is not read . At the last calculation step in register 18, the true value of the information previously read erroneously is determined. Through register 17, this information, under the control of unit 10, is recorded in a new memory area with further recourse to this area (Fig. 2, the error word correction mode).

In the event of an error when reading each word, block 13 defines it as an error of one bit of all words (case of failure of the output amplifier), block 10 organizes the reading of the vertical checksum of the memory area that contains errors. Further, reading of all words in a given memory area and their immediate summation within one word is organized with the subsequent subtraction of each bit amount from the checksum value.

Thus, at the last step in register 18, the true is determined: the value of all vertical bits read by the failed output amplifier of drive 5 previously. Through register 17, this information is written; It appears in the new memory area with a further reference to this area (Fig. 2, the multiple opsha correction mode).

The technical advantage of the proposed device is the fact that it provides an effective correction of erroneous information by endowing it with self-correcting functions of both one erroneous word and multiple errors

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Claims (1)

ERROR MEMORY DEVICE, containing the address register, multiplexer, comparison unit, drive, number register, logic unit, control unit and control unit, the output of the address register being connected to the first inputs of the comparison unit and multiplexer, and the input is the address input of the device, output the multiplexer is connected. to the first input of the drive, the first output of which is connected to the first input of the number register, the second input of which is connected to the first output of the logic block, the first input of the logical block, input, b the control window and the output of the number register are the information * output of the device, the information input of which is the second input of the logical unit, the first output of the control unit is connected to the third inputs of the number and logical unit register and the second input of the drive, the second output and the first input of the control unit are respectively control the output and input of the device, the second and third inputs are connected to the outputs of the comparison unit and the control unit, respectively, characterized in that, in order to increase the reliability of the devices , It introduces additional drives, control information register, the buffer register and the register addresses modified, the input of which is connected to the first output of the control unit, and an output connected to second inputs of the comparator and the multiplexer, ^you; the path of which is connected to the first inputs of the additional drives, one of the inputs of the control information register is connected respectively to the outputs of the additional drives and the second output of the logical unit, and the outputs are connected to the second inputs of the additional drives and the third input of the logical unit, the first output of the control unit is connected to the third inputs of the additional drives and a multiplexer, another input of the control information register and one of the inputs of the buffer register, the other inputs of which are connected respectively vhodom.registra of a second number and an information input device and an output connected to a third input mu drive. / 1 1128294 2