SU970479A1 - Memory with autonomous checking - Google Patents

Description

The invention relates to storage devices.

A self-monitoring memory device containing an address memory block connected to a first associative memory block, a second associative memory block one of the inputs of which is connected to the first input of the memory address block, a control block whose outputs are connected to control inputs associative memory blocks 1 The disadvantages of this device are complexity and low information capacity.

The closest technical solution to the invention is a self-monitoring memory device containing an address memory block connected to a first associative memory block, a second associative memory block, one of the inputs of which is connected to the first input of an address memory block, control block} The outputs of which are connected to the control inputs of the associative memory blocks, the first switch, the inputs of which are connected respectively to the first output of the decoder block and to the output of the address memory block, and vihody - to other inputs of the second associative memory block, the outputs of which are connected to the input of the decoder block and one of the inputs of the second switch, the other input of which is connected to the output of the decoder block, and the output to the input of the address memory block 2.

A disadvantage of this device is that, in case of cell bit failures of the address memory block, it is necessary to memorize in the second associative memory block the numbers of the failed bits and the values of the corresponding

15 information signals, which leads to an increase in the volume of the second, associative memory block, i.e. to the complexity of the device and reduce its information capacity.

20

The purpose of the invention is to simplify the device. ,

Claims (2)

This goal is achieved by the fact that the memory ycTpoiicTBO with autonomous control contains an ad hoc drive, amplifiers, a register of words, an address register, decoders, a control unit and associative drives, the control of which is connected to the outputs of the control unit 30. nor, and the address inputs with the address register inputs, the outputs of which are connected to the address inputs of the address accumulator, the information inputs and outputs of which are connected to one and the outputs and inputs of amplifiers, the other inputs and outputs of which are connected to one of the information outputs and inputs of the word register , the first control input of which is connected to the output of the first associative accumulator, the outputs of the second associative drive are connected to the inputs of the decoder, the input of the control unit is the control input of the device, encoders and a threshold element whose inputs are connected to other information loggers of the spruce register and information inputs of the first associative drive, and you encoder moves are connected to the information inputs of the second associative accumulator, the outputs of the decoder are connected to the second control input of the register, and the output of the threshold element is the control output of the device. The circuit diagram of the device is shown in it. The device contains the first associative storage unit 1 with informational: part 2, address part 3, outputs 4 and a control input, 5 address register 6, address pump 7, word register 8 executed on triggers with a counting input, amplifiers 9 block 10. controls, encoders 11, descriptors 12, threshold element 13, second associative accumulator 14 with indicative part 15 and address part 16, respectively, intended to record the numbers of failed bits and addresses of failed memory cells of the address accumulator. In the drawing, the address 17 and informational 18 inputs and information outputs of the device 19 are indicated. The device works in an inspired manner. Detection of bits in which the recorded information does not coincide with the nature of the failure is made during the recording of information in the address accumulator 7. At the same time, the address, entries to input 17, are recorded. into address part 3 of accumulator 1. The 3-writeable word from input 18 enters register 8 and is entered into accumulator 7 through amplifiers 9 and into information part 2 of accumulator 1. Then, the recorded word is read (with recovery of information) from accumulator 7 to register 8 If there is no failure in the cell 7 of the accumulator 7 at the address ycTct updated at input 17, or the nature of all the failures coincides with the recorded information, then in all bits of register 8 there will be a zero code. In this case, the contents of information part 2 of accumulator 1, corresponding to the state on input 17, and the address itself from address part 3 are erased. The input 17 is given the address of the next cell, similarly produces a new word. If there is a failure in the cell of accumulator 7 according to the adress set at input 17, the character of which does not coincide with the information written, then the corresponding bits of register B will contain a single code. The number of such bits is called the error multiplicity and denoted by: ; Further two cases are possible. ; If (where n is the number of word bits written to the address accumulator 7), then at the output of the threshold element 13 a single signal is output. It enters block 10: which blocks the deletion of the contents; in drive 1, corresponding to; the address set at input 17, i.e. Drive 1 stores the address of the drive cell 7, in which the apostles are marked, and the word to be written to this cell. The pains y, an output signal at the output of the element 13 is given a zero signal, arrivals into the block 10. At the same time, the block 10 produces a control sdgigish,: according to which the contents of the information part 2 corresponding to the address | on input 17, and the address itself from addressable part 3, the drive 1 is erased. One: at the same time, the S address part 16 of the accumulator 14 records the address, post, sent to input 17, and through the encryptor4 11 in Attribute part 15 records the numbers of the failed bits of the accumulator; l 7, the nature of the failures in which not, coincides with the information recorded in them. When reading information from a storage device at an address assigned to input 17, a simultaneous appeal is made to both drive 7 and associative nagofitel m 1 and 14. If the address is read, the word x, is stored in accumulator 1 then the transfer of information to register 8 from accumulator 7 is not arbitrary. At the same time, the contents of the information part 2 corresponding to the address specified at input 17 is output to output 4 and written to register B. After that, the read word goes to output 19. If the address of the read word is found in drive 14, then the register 8 reads information from the capacitor 7 through the amplifiers 9. Then the contents of the indicative part 15 on; the booster 14 corresponding to the address at the input 17 is transferred to the decoder 12. At the outputs of the decoder 12, a single code is formed in those bits, the nature of the failures in K6 TopLix does not matches the information recorded in them. This code is fed to the input of register 8 and inverts the correspondence of the bit. After that, the output 19 comes undistorted word. In the absence of the addresses 14 and 1 fed to the input 17 in the accumulators 14, the register-8 information from the accumulator 7 is read through the allocator 9 with the subsequent output of the device 19. In the proposed device, the storage capacity of the associative drive is reduced. The required volume of the primary part of the accumulator is more than d & a times less than in the known. Thus, the technique-economic advantage of the proposed device lies in its simplified R & D compared to the known. Claims of the invention A self-monitoring storage device containing an address storage device, amplifiers, a register of the word, an address register, decoders, a block yi. The controls and associative drives. The control inputs of which are connected to the outputs of the control unit, and the address inputs to the registrar register inputs, the outputs of which are connected to the address1SHM inputs of the address storage device, information inputs and outputs of which are connected to one of the outputs and inputs of amplifiers, the other inputs and rounds of which are connected to one of the information outputs and inputs of the word register, the first control which is connected to the output of the first associative accumulator, the outputs of the second associative accumulator Connected to the inputs of the di-diffuser, the control unit is the control input of the device, distinguished by the fact that, with a simple simplification, the encoders and the threshold element are entered, the input elements of which are connected to the other outputs of the register of the word and informshchionnymi the inputs of the first associative accumulator, where the encoder outputs are connected to the information inputs of the second associative accumulator, the outputs of the decoders are connected to the second control input of the word register, and the output of the threshold element is controlled We will output the device. Sources of information taken into account in the examination 1. Avtogyukoe certificate of the USSR 529490, cl. G & C 29/00, 1976. 2. Author's certificate. USSR 744738, cl. G 11 C 29/00, 1978 (prototype).