SU1109891A1 - Interpolating filter - Google Patents

Abstract

INTERPOLICERVE FILTER - containing a comparison element connected in series, the first input of which is an input of an interpolating filter, a limiter, a first integrator, a delay unit and an adder, as well as four subtractors, five scaling elements and a memory block connected to the output of the first integrator, which is also distinguished by the fact that, in order to improve the filtering accuracy, the second, third, fourth and fifth integrators, four multiplication units and the setpoint controller are introduced into it, the second integrator, the first subtraction unit and the first multiplier unit are connected in series between the output of the limiter and the second input. The accumulator, the third integrator connected in series, the second subtraction unit and the second multiplication unit are connected between the output of the first subtraction unit and the third input of the adder, the first scaling element connected in series the fourth integrator, the third subtraction unit and the third multiplication unit are connected between the output of the second subtraction unit and the fourth input of the adder, p Consequently, the second scaling element, the fifth integrator, the fourth subtraction unit and the fourth multiplication unit are connected between the output of the third subtraction unit and the fifth input of the adder, the memory unit connected in series, the output of which is connected to the second input of the first subtraction unit, the third scaling element, output which is connected to the second input C0 00 of the second subtraction unit, the fourth stabilization element, the output of which is connected to the second input of the third viiti unit, and the fifth scale y Aggregate element connected between the output of the second integrator and a second input of the fourth subtracting unit, the ramp output connected to second inputs of the first, second, third and fourth multipliers.

Description

The invention relates to radio engineering and can be used to delay the useful low-frequency component of the measured signals, which can be used, for example, in solving problems of late modeling, as well as in pre-history learning systems. An interpolating filter is known which contains delay blocks, the outputs of which through scaling blocks are connected to the summation block 13. The disadvantage of the interpolating filter is low filtering accuracy. The closest to the invention of the software of the technical entity is an interpolating filter containing a series-connected comparison element, a limiter, an integrator a delay- and adder unit, n memory blocks (n + 1) subtraction blocks, (n + 1) restriction blocks and ( n + 1) scaling elements, while the integrator output is connected to the second input of the comparison element, the first input of which is the input of the device of the ii memory block, the 1st subtraction block, the i-th limiting block and the i-th scaling element (, 2, ..p) are connected in series between the input meters of the device and the (1 + 1) -th input of the adder, (n + 1) -and the subtraction unit, (n + 1) -th limiting unit and (n + 1) -th scaling element are connected in series between the input of the device and ( p1 + 2) -th input of the adder, and the output of the delay unit is connected to the second input of the subtraction unit C21. A disadvantage of the known interpolating filter is the low filtering accuracy, since the refinement of the pre-smoothed signal x (tt) is performed by a finite number n + 1 of the differences between this signal and the input signal values of the device over the time interval Ct-t, t, and not on all the values of the differences of the corresponding continuous signals within the specified time interval. It is possible to increase the accuracy of the desired signal using a well-known interpolating filter by increasing the number (n + 1) of the differences taken into account, however, this is connected with an increase in the complexity of the device. Moreover, these differences are found with the input x values (, related to different points in time t-6-i within the time interval Ct-tr, tl and only one value of the preliminarily smoothed signal x (tt), thereby not using useful information on the values of preliminary The smoothed signal within the time interval tt-t, t1. The aim of the invention is to improve the filtration accuracy. I. The goal is achieved by an interpolating filter containing series-connected comparison element, the first input of which is the input of the interpolating filter, the limiter, the first integrator , the delay unit and the adder, as well as the chitfe of the slip block, five scaling elements and a memory block, the second input of the comparison element being connected to the output of the first integrator., the second, third, fourth and Fourth integrator, four blocks: multiplications and a setpoint controller, with the second integrator connected in series, the first subtraction unit and the first multiplication unit connected between the output of the limiter and the second adder input, the third integrator connected in series, the second subtraction unit and the second multiplication unit included between the output of the first subtraction unit and the third input of the adder, sequentially connected the first scaling element, the fourth integrator, the third subtraction unit and the third multiplication unit are connected between the output m of the second subtraction unit and the fourth INPUT of the accumulator, the second scaling element, the fifth integrator, the fourth reading block and the fourth multiplying block connected between the output of the third subtraction block and the fifth input of the adder, and the memory block connected in series to the second input of the first block subtraction, the third scaling element, the output of which is connected to the second input of the second subtraction unit, the fourth scaling

element 8 whose output is connected to WTO. The WOM input of the third subtraction unit, and the fifth scaling element are connected between the output of the second integrator and the second input of the fourth subtraction unit, and the output of the setter is connected to the second inputs of the first, second, third and fourth multiplication units.

In the drawing, a structural electrical interpolation filter circuit is presented.

The interpolation filter comprises a series-connected comparison element 1, a limiter 2, a first integrator 3, a delay block 4 and an adder 5, the output of the first integrator 3 being connected to the second input of the comparison element 1, the first input of which is the filter input, the second. 6, the input of which is connected to the output of the limiter 2, the first subtracting unit 7, the third integrator 8j the second subtracting unit 9, the first scaling element 10, the fourth integrator 11, the third subtracting unit 12, the second scaling An element 13, an fifth integrator 14 and a fourth subtraction unit 15, serially connected memory block 16, a third scaling element 17, a fourth scaling element 18, and a fifth scaling element 19 connected between the output of the second integrator 6 and the second input of the fourth block 15 the subtracts, the inputs of the third 17, the fourth 18 and the fifth 19 mass stabilizing elements are combined with the second inputs of the first, second and third blocks 7, 9 and 12 of the subtraction, respectively, the setting unit 20, the first, second, third and fourth blocks 21-24 multiplying, the first inputs The holes are connected to the outputs of the corresponding blocks 7, 9, 12 and 1 of the subtraction, the second inputs are connected to the output of the setting device 20, and the outputs are connected to the second, third, fourth and fifth inputs of the adder: 5

In the drawing, x (t) is the signal of the device; x (t-t) is the smoothed signal at the device output;

 Interpolating filter works as follows.

The input signal x (t) is pre-smoothed by a low filter.

frequency, consisting of the comparison element 1, the limiter 2 and the first integrator 3. To this end, the signal x (t) is fed to the first input of the comparison element 1, where the output signal of the low frequency filter x (t), which is output from the output, is subtracted from it the first integrator 3. The resulting difference

i "(t) x (t) - x" (t)

enters the input of the limiter 2, which can be implemented, for example, in the form of an amplifier with saturation. If the signal. (-) exceeds the value of the limiting voltage Jj, then in limiter 2 it is limited to this value. This can be represented by the expression

0

t) - fC 4t h4 «UHeS-S« l. Ujb eslts "4t).,.

where) - output signal limiter 2 i

The signal crCt) is fed to the input of the first integrator 3 and integrated in it. From the output of the first integrator of torus 3, it is pre-smoothed. by the low-frequency filter, the signal x (t) is fed to the input of the delay unit 4, where it is stored for the time interval b. Signal T) from the output

5 block 4 delay enters the first input of the adder 5.

The output of the interpolating filter is generated by refining the pre-smoothed signal.

0 x (t-t) according to the differences between the signs of this signal and the input signal of the device over the time interval It-t, tl.

To this end, the signal 5 (t) from the output of stroke of the limiter 2 is fed to

the input of the second integrator 6, in which it is integrated. The signal from the output of the second integrator 6 is fed to the input of the memory block 16, in which

50 it is delayed by the time interval t, and then to the input of the first subtraction unit 7, in which it is subtracted from the signal from the output of the second integrator 6.

The signal from the output of the first subtraction unit 7 is fed to the input of the third integrator 8, in which it is integrated. The signal from the output of the memory block 16 is fed to the input of the third scale tab 17 and is multiplied in it by the coefficient Ut ,. and goes further to the input of the second subtraction unit 9, in which it is subtracted from the signal from the output of the third integrator 8. The signal from the output of the second subtraction unit 9 is fed to the input of the first scaling element 10, multiplied therein by the factor jj 2 and fed further . the input of the fourth integrator 11, in which it is integrated. The signal from the output of the third scaling element 17 is fed to the input of the fourth scaling element 18, multiplied therein by a factor and sent further to the input of the third subtraction unit 12, in which it is subtracted from the output signal of the fourth integrator 11. The output signal of the third subtraction unit 12 is fed to the input of the second scaling element 13, is multiplied in it to the coefficient Jfi 3 and is fed further to the input of the fifth integrator 14 in which it is integrated. The signal from the output of the fourth scaling element 18 is fed to the input of the fifth scaling element 19, multiplied in it by a factor and fed further to the input of the fourth subtraction unit 15, in which it is subtracted from the signal from the output of the fifth integrator 14. The gain factors of the second, third The fourth and fifth integrators 6, 8, 11, and 14 are set to one. The transfer function of the circuit consisting of blocks 6, 7, and 16 has the form) / is the transfer function of the integrator; - the transfer function of the memory block 16, and the corresponding impulse characteristic of the V-, / CLEANER, © CAM Cho if (2) The transfer function of the circuit consisting of blocks 6, 7, 8, 9, 16 and 17 has the form W., and the corresponding impulse response (B, Cd:., "" "CAM t The transfer function of a circuit consisting of blocks 6, 7, 8, 9, 10, 11, 12, 16, 17 and 18 has the form Nk / 2 () ..e .. "P-, and the corresponding impulse response if (e) {o:" SAI The transfer function of the circuit, consisting of blocks 6-19, looks like) -e and the corresponding impulse response e if OidA-; () - CAM. (5) The signals from the outputs of blocks 7, 9, 12 and 15 of the subtraction arrive at the first inputs of the corresponding blocks 21-24 multiplication, multiplied in them by the coefficients to, t, f and t, set from the output of the setpoint 20 to the second inputs of blocks 21 -24 multiplications are fed further to the second, third, fourth and fifth inputs of the adder 5, with which they are summed, resulting in a signal ux (tC). The impulse response of the circuit, whose course is the input signal d (t) of the second integrator 6, and the output is the result of summing x (tt), has the form of DY) o (e, ", (e"% ()), "esAM lO, "CAM -ftyt, the output ux (t-lr) signal of this circuit is formed in accordance with the expression (t-tbx4t-t) vaf (). 4 LxMmi-ft ar (; coefficients to, Ji, g, g) Set at the output of the setpoint 20 so as to ensure

Claims (1)

(57.) INTERPOLING FILTER, - containing a series-connected comparison element, the first input of which is an input of an interpolating filter, a limiter, a first integrator, a delay block and an adder, as well as four subtraction blocks, five scaling elements and a memory block, while the second input of the element of comparison is connected to the output of the first integrator, which differs in that, in order to increase the filtering accuracy, the second, third, fourth and fifth integrators, four multiplication units and a master are introduced into it, while the second integrator, the first integrator, the first subtraction unit and the first multiplication unit are connected between the output of the limiter and the second adder input, the third integrator is connected in series, the second subtraction unit and the second multiplication unit are connected between the output of the first subtraction unit and the third adder input, the first scaling element is connected in series, a fourth integrator, a third subtraction block and a third multiplication block are connected between the output of the second subtraction block and the fourth adder input, followed by the second scaling element, the fifth integrator, the fourth subtraction unit and the fourth multiplication unit are connected between the output of the third subtraction unit and the fifth input of the adder, and the memory unit is connected in series, the output of which is connected to the second input of the first subtraction unit, the third scaling element, the output which is connected to the second input of the second subtraction block, the fourth__ scaling element, the output of which is connected to the second input of the third subtraction block, and the fifth scaling element us between the output of the second integrator and a second input of the fourth subtracting unit, the ramp output connected to second inputs of the first, second, third and fourth multipliers.