SU1092728A1 - Self-diagnosis calculating apparatus - Google Patents

Abstract

COUNTABLE DEVICE WITH CONTROL BY SELF, containing a counter, a device for generating a parity feature, a trigger, the output of which is connected to the input of a comparison element, characterized in that, in order to improve the control speed, a modulo-sum element is entered into it, the output of which is connected to the second input the comparison element, and the bitwise inputs are connected to the outputs of the corresponding counter bits and the first inputs of the parity feature generator, the second and third inputs of which are connected respectively to the first and the second inputs of the counter, and the output with the counting trigger input, the zeroing input of which is connected to the second input of the counter, the parity feature generation device contains an additional trigger, element 2I-OR and a decoder, the inputs of which are connected to the first inputs of the parity characteristic generation device, and the output is connected to the first input of the first element AND element 2I-OR, the output of which is connected to the output of the device for generating the parity feature, the second input of the first and the first input of the second element AND element 2I-ML11 (L are combined a row are connected to the counting input of the additional flip-flop C and a second input device generating a parity indication, a third input coupled to the reset input of additional flip-flop, whose output is connected to the second input of the second AND-2I 1SHI element.

Description

The invention relates to a pulse technique and can be used in computing and measuring devices. A device for controlling a counter is known, which contains a counter, AND elements, a to trigger. However, the device does not have sufficient functionality. The closest technical solution to the proposed is a counting device with self-control, containing a counter, a device for producing a parity feature, a trigger, the output of which is connected to the input of the comparison element G 2 3. The device also has a relatively low speed. The purpose of the invention is to increase the speed of control. The goal is achieved by the fact that a self-checking counting device containing a counter, a device for generating a parity attribute, a trigger whose output is connected to the input of the comparison element, has modulo-two summing element, the output of which is connected to the second input of the comparison element, and the inputs bit by bit are connected to the outputs of the corresponding bits of the counter and the first inputs of the yoke output of the parity feature, the second and third inputs of which are connected respectively to the first and second inputs of the counter, and the output from the counting input the flip-flop, the zeroing input of which is connected to the second counter input, the parity feature generation device contains an additional trigger, element 2И-OR and a decoder, whose inputs are connected to the first inputs of the parity characteristic device, and the output is connected to the first input of the first element And element 2I- OR, the output of which is connected to the output of the device for generating the parity feature, the second input of the first and the first input of the second element AND, element 2I-1ShI are interconnected, connected to the counting input of an additional t the rigger and the second input of the device for generating the parity feature, the third input of which is connected to the zeroing input of the auxiliary trigger, the output of which is connected to the second input of the second element AND element 2I-1-SHI. Figure 1 shows the block diagram of the counting device with self-control; 2 is a time diagram of the operation of the device. The counting device with self-control contains a counting 1, a device for generating a parity attribute 2, a modulo-two summation device 3, a counting trigger 4, a comparison element 5, links 6-8, a decoder 9, a second counting trigger 10, and an element P 2-OR The output of counter 1 is connected to the input of the decoder 9 and the input of the device 3 modulo-summing two, the output of which is connected to the input of element 5 is compared}, the second input of which is connected to the output of counting trigger 4, the input of which is connected to the output of element II 2IILI, the first the inputs of which are connected The first inputs of the element 11 2I-LII are connected respectively to the output i of the second counting trigger 10 by the output of the decoder 9. The trigger enters through the communication line and the first input of the counter and the first input of the second counting trigger 10, the second input of which is connected to the second input of the counter. 6, installation in. the zero of the counter, the second counting trigger 10 and the counting trigger 4 is carried out on the communication line 7, the fault signal is removed on the communication line 8. The device operates in the following way. Initially, all of the memory elements are reset. The first input of the counter and the first input of the second trigger 10, operating in the frequency division mode, receive triggering signals. The counter counts the incoming pulses and its expired code enters the input of the device 3 modulo two and the decoder input 9. Dephafrator 9 detects all code combinations, in which the number of ones, starting with the least significant bit and before the first code in the code, is even . The number of combinations of output signals of the counter, to which the decoder 9 enters the signal, is determined by the expression - m-2 N. i :: 0 de n - the number of bits of the counter j m -g- for n even; 3 n-1 odd. For example, for a five-bit chick in accordance with the specified razheniem. 10927284 The bit code of the counter, at which the decoder generates a signal, and the count — the number of trigger signals of the counter you have output for this device are given in the tabl lCB,

The operation of the device for a five-bit counter is illustrated by the timing diagram shown in Fig. 2, the following notation is taken on the H timing diagram:

T1 - counting trigger element T 2 - second counting trigger

(item 10); Exit Osh - output decoder (element 9); Cm.M2 - Summation scheme by

module two (element 3); VH.V - the output of the first circuit AND

(Element 11);

ZYH.V2 - the output of the second circuit AND

(Element 11);

1 -t SP - counter output code; Alarm-triggering signal

counter.

The counting trigger T1 (element 4) can be started from the output of the second IO counting trigger and from the output of the decoder 9. Through the element 11 2ILI, the corresponding output signals of the triggering of the counting trigger T1 in FIG. 2 are shown in l Out x and B and Out .V2 and the resulting signals on the TI.I bus.

When the counter is working correctly, the signals from the output of the device 3 modulo two and from the output of the counting trigger 4 are imverse, and the comparison element 5 does not cause a fault signal

When a counter malfunctions, such as a skip trigger signal or an incorrect output code is generated by the counter, the inversion of the output signals from the modulo two summing circuit and the output of the counting flip-flop T1 is violated. The summation circuit generates a fault signal.

The technical and economic effect of this device is to increase the control speed. In the known device, the malfunctions of the triggers in the bits of the counter are detected with a delay of several trigger signals relative to the time of the malfunction. In this device, the counter malfunction is detected immediately after its appearance, i.e., at the moment of the trigger pulse, the reaction (output code) of the counter to which turned out to be incorrect. This creates the possibility of complete elimination of the error, which is especially important when using a counting device in control signal generation devices.

fs (8.2

Claims (1)

ACCOUNTING DEVICE WITH SELF-CONTROL, containing a counter, a device for generating a parity sign, a trigger, the output of which is connected to the input of the comparison element, characterized in that, in order to increase the speed of control, a modulo-two summing element is inserted into it, the output of which is connected to the second input of the element comparisons, and the inputs are bitwise connected to the outputs of the corresponding bits of the counter and the first inputs of the device generating the sign of parity, the second and third inputs of which are connected respectively to the first and second the counter inputs, and the output with the counting input of the trigger, the zeroing input of which is connected to the second input of the counter, the device for generating a parity flag contains an additional trigger, a 2I-OR element and a decoder, the inputs of which are connected to the first inputs of the device for generating a parity flag, and the output is connected to the first the input of the first element 11 of the element 2 AND-OR, the output of which is connected to the output of the device generating the sign of parity, the second input of the first and first input of the second elements AND element 2I-OR are interconnected, connected s with the counting input of the additional trigger and with the second input of the device for generating a parity flag, the third input of which is connected to the input of zeroing the additional trigger, the output of which is connected to the second input of the second element AND of the 2 AND-OR element. SU. „. 1092728 fi"!