RU1791957C - Device for pulse sequence control - Google Patents

Abstract

The invention relates to the field of automation and instrumentation. The aim of the invention is to increase reliability and noise immunity. For this purpose, a memory block 5, a first and second inverters 4.14, a first capacitor 2, and a first capacitor 2 are introduced into a device for monitoring a pulse sequence containing an input bus 2, two elements OR 10.17, elements 15, 16, a counting trigger 3. the memory unit 5 comprises a pulse-to-voltage converter 6, a pause to voltage converter 7, a second and third capacitors 11, a controlled one-shot oscillator — a pulse-width driver 8, a controlled single-vibrator-shaper 9 of the pause duration. The goal is achieved due to the fact that each period (pause and pulse) of the monitored sequence is compared with the previous one entered into the analog memory unit, while the output of the device does not overlap for a pause time, which prevents the passage of noise, and in the case of a skipped pulse, an impulse with previous duration. Therefore, the number of information pulses at the input and output of the device is equal to each other (although the output sequence is delayed by one pulse relative to the input) both in the absence and upon presence of failures at the input,. , „, AJ3 SL with

Description

The invention relates to digital automation and instrumentation and is intended to recover information in the event of a malfunction (skipping or counting of sequence pulses),

Known devices for monitoring the sequence of pulses and correcting failures by a pulse counter (see AS USSR No. 1347TV2G No. 13.45340, No. 1307581, No. 1307580, {x | N% 75% 2.1 Y298898, No. 1298895, No. 128559 t Ш277Ш, No. 1279200, No. 1192139, No. ff75029, fiaT, USA G Ts3898444, Japanese Patent, Sellers F. Methods for detecting errors in the operation of computers, M., Mir,

 1972; Losev V.V., Yakovlev D.O. Correction of failures of recalculation schemes. Automation and Telemechanics, No. 5, 1971). .

However, these devices are complex (especially using redundant information) and therefore, in turn, require protection from failures. In addition, most of these devices only register failures, and those that can be corrected by a glitch are complex (due to the presence of a digital element, they can also be used or similar devices). Many of these devices require a check sequence.

 impulses; in which there should be no failures (omissions, counts) ..-:.

The closest in technical essence to the proposed device is device 2, which contains a counting trigger, five AND elements, two OR elements, two input buses, two counting triggers with installation inputs, a delay element and an output bus. However, this device, requiring the presence of two sequences of pulses (controlled and reference): does not allow correcting failures of the controlled sequence.

The aim of the invention is to increase the reliability and noise immunity by co-correcting the failures (counts and miscalculations) of the controlled sequence without using a reference pulse sequence.

The essence of the invention consists in storing the previous period (pause and pulse durations) and in one case of its change due to loss or interference in the next period, correction is made by repeating the previous period.

In order to solve this problem, a memory block, a first and second inverters and a first capacitor are introduced into a device for monitoring a pulse sequence comprising first and second AND elements, a first and second OR element, a counting trigger, as well as an input and output bus. contains a pulse width to voltage converter, a second and third capacitors, a controlled one-shot driver, a controlled one-shot driver, and a pause duration of 4, the input bus being connected inena with the first (control input of the pulse width converter) is directly, and with the first (control) input of the pause timer is through the first inverter, the counting input of the counting trigger is connected to the output bus through the first capacitor, the direct output of the counting the trigger is connected to the second (fault), and the inverse output to the third (fault) inputs of the pulse width and pause voltage converters, outputs

which are connected to the first (control) inputs of the controlled one-shot drivers of the pulse duration and pause, the second (start) input of the pulse width generator via the second capacitor is connected to the inverse output of the breaker of the pulse duration and, in parallel, with the second input of the first OR element, the first input of which is connected to the output of the driver of the pulse duration, and the output to the second inputs of the first and second elements And, and the first input of the first element And through the second inverter, and the first input of the second AND element is directly connected to the input bus, the outputs of the first and second AND elements are connected respectively to the first and second inputs of the second OR element, the output of which is the output of the device, the output of the first inverter through the third capacitor is connected to the second (starting ) the input of the shaper for the duration of the pause. The output of the first AND element can be used to connect a failure (skip) counter

input pulse sequence.

The proposed device allows you to correct failures (missing pulses or extra pulses) of the controlled sequence, at the same time signaling the presence of these, failures by the appearance of pulses at the output of the first element I.

According to the criterion, significant differences should be noted that we did not find technical solutions containing features similar to those claimed.

. The drawing shows a functional diagram of the claimed device.

The device for monitoring the pulse sequence contains an input bus 1, a first capacitor 2. counting trigger

3, the first inverter 4, a memory unit 5 including a pulse width to voltage converter 6, a pause to voltage converter 7, a controlled one-shot driver 8 of a pulse duration, a controlled one-shot driver 9, a pause duration, first OR element 10, second capacitor 11, third capacitor 12, output bus 13 of the memory unit, and also an output device including a second inverter 14, first and second elements AND 15, 16, a second element AND 17, output bus 18 (and also complement output bus 19 for connecting a failure counter),

The input bus 1 is connected to the first (control) input of the converter 7 through an inverter 4. The counting input of the counting trigger 3 through the first capacitor 2 is connected to the output bus 18 of the device, the direct output of the trigger 3 is connected to the second (reset) inputs, and inverse output - to the third (discharge) inputs of the converters 6 and 7, the outputs of which are connected respectively to the first (control) inputs of the drivers 8 and 9. The second (start) input of the driver 8 through the second capacitor 11 is connected to the inverse output of the driver 9 and, in parallel - a second input of the first OR gate 10 having a first input connected to the output driver 8, and the output on the output bus 13 of the frame 5 (the joining elements 6-13). The second (start) input of the driver 9 through a capacitor 12 is connected to the output of the first inverter 4. The input bus 1 is also connected to the input of the second inverter 14 and, in parallel, to the first input of the second element And 16, the first input of the first element And 15 is connected to the output the second inverter 14, the second inputs of the elements And 15, 16 are connected to the output 13 of the storage unit 5, the output of the first element And 15 is connected to the first input of the second element OR 17 (and, in parallel, to the additional output bus 19), the second input of the second element OR 17 connected to the output of the second element And 16, and the output is the output of the device.

The device of FIG. 1 (taking into account examples of implementation of figure 2, 3) works as follows ..

The monitored signal U1 and the signal U13 from the output 13 of block 5 are supplied to the inputs of the elements of the device containing the elements 14-17, the output of which is the output signal of the device U18. The truth table of the specified device is

U1 1 1 O O

U13

 1 o 1 o

U18 1 O 1 O

that is, there is no output signal (U) if there is interference on the input bus 1 (U 1 1), but logic O is on the control input (output 13 of block 5). On the contrary, the output signal is (U) if the input bus 1111 1 and at the control input or only at the control input (in case of failure - the absence of the next pulse of the sequence on bus 1). In the latter case, i.e. when a pulse of the controlled sequence drops out on the input bus 1, the pulse of the controlled sequence, which is absent and therefore does not go to output 18, is replaced by a pulse coming from the output 13 of block 5 and having a pulse duration and pause rn, like the previous pulse on the input bus 1. ..

The conversion of the pulse duration value and the voltage and storing of this voltage during one period of the controlled sequence is performed by the converter 7 along the trailing edge of the next pulse of the controlled sequence (i.e., the leading edge of the same pulse after inverter 4). In this case, the pulse duration (pause) is stored alternately on the capacitors (C1) of the converter 6 (7), in accordance with the “alternating reset pulses generated by the capacitors (C2) of the converter 6 (7) from the output pulses of the counting trigger 3 controlled by , pulses from the output 18 of the device through the capacitor 2 (see Fig. 1).

For example, for the shapers 6, 7, the signals on the capacitors C1, transmitted to the output of the converter via diodes and a repeater, form a constant (at least for one or two periods) signal that controls, for example, the pulse width of the shaper 9 (equal to rn) removed from the inverse output of this driver (see FIG. 3) and supplied to the second input of the first element OR 10 and at the same time with its trailing edge (through the second capacitor 11) triggering a similar pulse shaper (gi) 8. The need for two shapers x - 8. for Hz and 9 for gp - is explained by the need for independent adjustment of gi and gp values. The control of these formers must be continuous (they must be constantly ready for operation), for which, for example, in the example of implementation, converters 6, 7 have two capacitors C1: while there is a reset and an increase in voltage on one of them (during time gi, mn) a constant control signal is supplied to the input of the shaper 8 (9) from another capacitor, which is achieved by alternately supplying fault signals from the outputs of the counting trigger 3.

Thus, if, after a pause of rp, a malfunction occurs in the controlled sequence of pulses, that is, the next pulse does not arrive at input bus 1, then at output 18 it will be replaced by a pulse of duration t from output 13 of device 5. Registration of failures (omissions of pulses) is carried out at the output 19 of the first element And 12, which can be connected to the counter failure sequence of pulses supplied to the input bus 1.

It should be emphasized that the device delays the sequence by one pulse, but does not lose the first pulse, since the first long pause will be perceived by it as a pulse skip and one pulse will be added at the end of the sequence. It should also be noted that, as can be seen from the object of the invention, this device, without using (for the sake of simplification and to avoid imposing additional requirements on the input signal) redundant information, cannot accurately reproduce. keep a missed momentum if nothing is known about it in advance. In this case, instead of the missed pulse, you can either reproduce the average (in duration) pulse, or repeat the previous pulse (which is used in this device). In the initial period (power is on, there are no signals yet), the device could be blocked until the first signals appear, however, then the first increase in the pause will be regarded by the device as a pulse skip, as a result of which the device will add one pulse, which will be superfluous.

Claims (1)

The proposed device compares favorably with the prototype and (known) analogs 1 in that, in addition to registering faults (gaps of pulses) of the pulse sequence, it corrects this sequence so that the number of pulses of the input (undistorted) sequence, despite subsequent gaps and interference, remains constant. At the same time, the device does not require the use of forward and reverse codes, rather complex digital comparison devices, etc. The claims A device for monitoring a pulse sequence containing an input bus, two OR elements, wherein the inputs of the first OR element are connected to the outputs of the AND elements, the output to the output the device bus, as well as a counting trigger, characterized in that, in order to increase reliability and noise immunity, a memory block, a first and second inverters and a first capacitor are introduced into it, the memory block comprising a pulse width to voltage converter, a pause to voltage converter voltage, second and third capacitors, controlled single-vibrator-shaper of pulse duration, controlled single-vibrator-shaper of duration of a pause, and the input bus connected to the first (control ) Input converter pulse duration to voltage directly, and with the first (control) input of the pause-to-voltage converter, through the first inverter, the counting input of the counting trigger via the first capacitor is connected to the output bus, the direct output of the counting trigger is connected to the second (resetting), and inverse output to the third (fault) inputs of the duration converters pulse and pause voltage, the outputs of which are connected respectively to the first (control) inputs of the adopted single-shot-vibrators pulse duration and pause, starting input of a controlled single-vibrator-shaper of pulse duration through a second capacitor is connected to the output of a controlled single-vibrator-shaper of pulse duration and to the second input of the second OR element, the starting input of the controlled single-vibrator-shaper of the pause duration through the third capacitor is connected to the output of the first inverter, and the output of the controlled single-vibrator-shaper of the pulse duration is connected to the first input of the second OR element, the output of which is connected to the first inputs of the first and second AND elements, second inputs respectively through the inverter and 5 are directly connected to the input bus, the outputs of the first AND element, the first OR element, are the outputs of the device.