SU1049922A1 - Device for computing current estimation of average value - Google Patents

Description

The invention relates to computer science and computing and can be used for hardware analysis of random processes and statistical processing of hjaccHBOB data.

A digital smoothing device is known, which contains an adder, a block for setting division factors, a second adder, a register, a count counter, two decoders, AND, OR elements, a character trigger and a control block l,

The drawback of the device is the low convergence rate of the calculated average value.

Closest to the invention in its technical essence is a device for calculating a current estimate of the average value, comprising the first shift register, the first one. an adder, a group of shift registers, a second shift register, a second adder, a control unit whose outputs are connected to the corresponding synchronization inputs of the shift registers 2.

The disadvantages of the known device are low speed and complexity.

The purpose of the invention is to increase the speed and simplify the device.

The goal is achieved by the fact that in the device for calculating the current estimate of the average value containing the shift register, the outputs of which are connected to the corresponding information inputs of the first adder, the second adder and the control unit consisting of a trigger, the first OR element, the count counter, the coefficient setting node division, a group of reference elements, a counter, two elements AND, a counter-divider, a pulse generator, the output of which is connected to the first inputs of the first and second elements AND, the output of the counter-sharing It is connected to the installation input in the trigger, the installation input of which is combined with the input of the counter of counts and connected to the output of the first OR element whose inputs are the information inputs of the device, the outputs of the counter of counts are connected to the corresponding inputs of the division factor setting node whose outputs are connected with the first inputs of the comparison elements of the group, the second of which are connected to the outputs of the counter, the ciiiHx-down input of which is connected to the output of the first element AND, the output of the trigger is connected to the second input for the second element And, the output of which is connected to the input of the counter-divider, the first input of the shift register is connected to the output of the second element AND, the second element OR is entered into the control unit

| information inputs of the shift register are connected to the corresponding outputs of the second adder, the inputs of which are information inputs of the device, the synchronization input and the 5 input of the installation in the O rrvrgo adder are connected respectively to the outputs of the first and second elements OR, the output of the second element AND is connected to the first input of the register o the shift, the second input of which is connected to the output of the first element OR, the output of the counter-divider is connected to the input of the installation in О of the counter, the output of the trigger is connected to the second input of the first element The input AND, the outputs of the comparison group elements are connected to the corresponding inputs of the second OR element, the outputs of the first adder are information outputs of the device.

FIG. 1 is a block diagram of the device; in fig. 2 - control unit.

The device contains the second adder 1, the control unit 2, the shift register 3, the first adder 4. The control unit 5 2 contains the first element OR 5, the trigger 6, the counter 7 samples, the node 8 specifying the division factors, a group of comparison elements 9, the counter 10, the first the element And 0 11 / second element And 12, the generator 13 pulses, the counter-divider 14, the second element OR 15 ..

The device is based on pea. LIZATION ALGORITHM

- i / and

-one.

5 „1 1 cu1-a1 04 1

Oj

where XJ - j is the countdown of the input function;

5i is an estimate of the current average value;

if summant is included in the amount

CO, otherwise

The device works as follows.

Samples of the input function in the form of a parallel code N are received

input bus simultaneously on

enter the adder 1 and the control inputs of the control unit 2. The value of the next Ni sample in adder 1 is summed with its contents. AT

block 2 control / on the element code, OR 5, a pulse is generated, which cocks trigger b and at the same time increases the contents of the counter 7 samples by one. The signal from the output of the element OR 5 is rewritten.

the contents of the adder 4 into the shift register 3. With the same signal, the adder 4 is reset to the zero state. A count counter 7 controls the coefficient setting node 8

division. Each new state of the 7 counts counter corresponds to a certain combination of code points, the number of which determines the number and values of summats, which approximate the linear averaging operator with a given accuracy: i.e. 5k can be represented in the form / sum of binary discretes - n-i 7Г 21 OS, where o - takes 1 if summant is included in the sum approximating 1 / N, or O otherwise. In block 2 of control, trigger 6 opens element 11 and element 12 as well. G output of generator 13 through open element 11 of pulses arrives at the input of counter 10, and through element 12 of the output of divider 14. At the time the current equals A counter 10 with one of the code layers of the node 8 specifying the division coefficients at the i-th output of the comparison elements 9 forms a pulse (which passes through the OR element 15 to the third input of the control unit 2). This signal, generated at the output of block 2, records the contents of the shift register 3 into the second adder 4, where the current code is summed with the contents of the adder: 4. The impulse from the output of the And 12 element is fed to the second output of block 2 and the input of the counter-divider 14. Köe counting factor K counter-del1; ate 14 equals the number of bits AND register 3 shift without taking into account the additional bits. Thus, from the outputs of control unit 2, outputs from a series of control pulses. Hp; if the shift pulses are equal to the number 1 of the bits of the register 3 shift the number of pulses and their distribution in time is determined by the node 8 setting the division factors. At the moment of equality of the number of shifting pulses arriving at the register 3, the ratio of the counter-divider 14, the latter generates a signal that returns the trigger 6 to the initial state. Trigger 6 closes the elements, both 11 and 12. Once a signal from the output of counter 14, the counter 10 clears the zero state, preparing it for the next operation cycle. Thus, the content of the first adder 1 is successively divided in the shift register 3 by the coefficients 2, 2, 2, 2, 2 ..., where the bits of the register 1 3 shift are found. According to the signals arriving at the control input of the adder 4, it is ensured that the corresponding summers are recorded in the adder, where they are summed. By the end of the operation of the counter-divider 14, the shift register 3 is zeroed (meaning the number of main digits of the register), and in the adder 4 a sum of N .11 G x 2 a is fixed; . IrO The maximum calculation time for the current estimate of the average value in ticks is. where / 2 (3 is the period of the reference frequency; h is the number of main bits of the register. 3 shift. In the known device 3nV, the ratio f shows the gain in speed, i.e. the proposed device reduces the computation time by 66%. Thus, the introduction of new links into the device for calculating the current estimate of the average value allows increasing the speed of the device and simplifying it.

Claims (1)

A DEVICE FOR CALCULATING A CURRENT ASSESSMENT OF THE AVERAGE VALUE, containing a shift register, the outputs of which are connected to the corresponding information inputs of the first adder, a second adder and a control unit consisting of a trigger, a first OR element, a count counter, a unit for specifying division factors, a group of comparison elements, a counter, of two And elements, a counter-divider, a pulse generator, the output of which is connected to the first inputs of the first and second And elements, the output of the counter-divider is connected to the installation input at 0 trigger a, the input of unit 1 of which is combined with the input of the counter of reports and connected to the output of the first OR element, the outputs of which are information inputs of the device, the outputs of the counter of samples are connected to the corresponding inputs of the unit of reference division factors, the outputs of which are connected to the first inputs of the comparison elements groups, the second inputs of which are connected to the outputs of the counter, the synchronizing input of which is connected to the output of the first element And, the trigger output is connected to the second input of the second element And, the output of which connected to the input of the counter-divider, the first input of the shift register is connected to the output of the second AND element, characterized in that, in order to improve performance and simplify the device, the second OR element is entered into the control unit, the information inputs of the shift register are connected to the corresponding outputs of the second adder, the inputs of which are information inputs of the device, the clock input and input ζ of the installation in О of the first adder are connected respectively to the outputs S of the first and second elements OR, the output of the second ment And is connected to the first input of the shift register, the second input of which is connected to the output of the first OR element, the output of the counter-divider is connected to the input at the counter 0, the trigger output is connected to the second input of the first AND element, the output of the group comparison elements is connected to the corresponding inputs of the second OR element, the outputs of the first adder are information outputs of the device. 1049922 A 1049922 2 (the information inputs of the shift register are connected to the corresponding outputs of the second adder, the inputs of which are the information inputs of the device, the clock input and the installation input at 0 of the first adder are connected respectively to the outputs of the first and second elements OR, the output of the second element AND is connected to the first input of the register shift, the second input of which is connected to the output of the first element OR, the output of the • counter-divider is connected to the input of setting _h at 0 of the counter, the trigger output is connected to the second input of the first ele And, the outputs of the group comparison elements are connected to the corresponding inputs of the second OR element, the outputs of the first adder are the information outputs of the device: Fig. 1 shows a block diagram of the device; Fig. 2 - control unit. The device comprises a second adder 1, a control unit 2, a shift register 3, a first adder 4. The control unit 25 2 contains a first OR element 5, a trigger b, a counter 7 samples, a node 8 for setting the division factors, a group of comparison elements 9, a counter 10, the first element And 11, the second element And 12, the pulse generator 13, the counter-divider 14, the second element OR 15., The operation of the device is based on the implementation of the algorithm