SU568170A2 - Communication channel condition monitoring device - Google Patents

Description

Comparison element 9, element OR 10, counter 11 intervals, two prohibition elements 12.13, shift register 14, trigger 15, form of 16 pulses, bit counter series-connected frequency divider 18, control counter 19, delay element 20, whose input is also connected to the first inputs of the keys 21, the reading unit 22, the block 23 of pulse counters, the decoder 24, the block 25 of the OR elements, the outputs of which are connected to the second inputs of co-coded keys 21 | The output of the impulse compressor 16 is connected to the second input of the discharge counter 17 through delay element 26 and to the reset input of read unit 22 directly, and the input from the frequency divider 18 is fed from the input 27. Receiver 1 ct holds multipliers 28, integrators 29 and comparison element 30 .

The device works as follows.

The device receives a useful signal and interference. In multiplier 28, the noisy signal is multiplied by the reference single and zero signals. Random values from the integrator® 29 are fed to down-circuits 2,3. If these signals are greater than the threshold, signals from a single output of coincidence circuit n 4 appear on single outputs of the release circuits 2, 3, from which I send I SNO of the first kind to the element OR 1 O. If the signals at the inputs of the trigger circuits 2 and 3 are less than the threshold, at their zero outputs, signals appear that arrive at the coincidence element 5, from which the SNO of the second kind arrives at the OR 10 element. The signal that appeared at the output of the OR OR signal goes to the prohibiting entry of the prohibition element 12, thereby prohibiting the passage of the TI from the input 27 to the counter 11. set to zero.

If on the next cycle of operation of the device, the AtoNS does not arrive at the prohibiting entry of prohibition element 12, the first TI passes to the counter 11. At the next clock cycle, if at the output of the element I.PI 10 there is no SNO, the second TI is received at the counter 11, and so on. until the output of the element OR 1O does not produce a pulse of AtoN. Through X, adducts after the appearance at the output of the AND / 1I 10 element of the first CHO pulse, this pulse appears at the output of the shift register 14 and enters the zero input of the trigger 1 which passes from one to the zero state, and the potential on the inhibitory

in the element of prohibition 13 disappears. Through the prohibition element 13 pa bit counter 17 passes TI. НСЭ 3e ag + l-BDvr cycle, if, during this time, the SNO pulses, except for the first one, did not appear, the output of the counter 11 is a signal that arrives at the single input of the trigger 15, which goes into the single state. From the trigger 15, the prohibiting entry of the bar 13 element receives a high potential, which prohibits the passage of the TI to the bit counter 17.

At the same time, the shaping device 16 by the potential difference® at the output of the trigger 15 generates a pulse, which sets the counter 17 to the zero state.

If the interval between the first and the following AtoN is not greater than., Eg the device’s cycles operate as follows.

The first impulse of the AtoN through: GYText appears at the output of the shift of the register 14, arrives at the zero input of the trigger 15 and translates it into the zero state. At the output of the trigger 15, the high potential disappears, the prohibition element 13 is opened and the discharge counter 17 passes the TI. Before the signal appears through Hdoy-1 clock cycles at the output of the counter, the prohibiting input of the prohibition element 12 enters the second AtoNW, which also goes to the shift register 14 and resets the counter

11 in zero state. If the interval between the second and third CHO is also less than the signal at the output of the counter 11 does not appear, and the trigger 15 remains in the zero state. Through the open element: prohibition 13 all the time passes 111. Thus, as long as the interval between incoming SNO pulses from the element OR 1O is no longer. 96 jao, the element of the prohibition 12 receives the AtoN belonging to the same package of AtoNU of a certain length, the bit counter 17 passes through the TI,

and the counter counts the packet length.

Let the last Atomenie belonging to this packet arrive at a tick at the prohibiting entry of prohibition element 12. Through the clock cycles, the AtoNW arrives at the output of the shift register 14 and arrives at the zero input of the trigger 15. At the counter 17, another TI enters through the open element of the prohibition 13. Since the considered AtoN is the last one in the packet, the interval between it and the next AtoN is more than 3t 20. Therefore, in the next 36, 1-th cycle after the receipt.

At the last CHO of this packet, a pulse appears at the output of counter 11. This impulse arrives at the single input of the trigger 15 and translates the ei-o into a single state. An output of trigger-fipa 15 appears in the bbic lottery, which closes prohibition 13. to zero state.

Thus, the TI number recorded in the bit counter 17 corresponds to the length of the SNO packet. In the dependencies of the lead, the ranks of this number on the NECM from the outputs of the readout block 22 a pulse appears, which is entered into the block 23 of the pulse counter.

At the end of the control interval, the value of which is determined by the division factor of frequency divider 18 and the capacity of the control counter 19, the contents of block 23 are read from the pulse. Depending on the contents of block 23, one of the outputs of decoder 24 receives a signal that 25 post; falls on the corresponding key 21.

At the end of each control interval, the control signal from the control counter 19, applied to the first inputs of the keys 21, and the output of one of the keys, appears the signal supplied from the corresponding output of the balance 25, which signals the state of the communication channel. By this

the same signal from the control SKT.ch.ch 19 through the delay element 20, the block 23 sets the pulse rate to the bullet state.

The form / fa invented and

A device for monitoring the state of;) communication by author. St. No. 537448, characterized in that, in order to improve the control accuracy, a serially connected frequency divider, a control counter, two delay elements, the input of the first of which is also connected to the first inputs of the newly entered corresponding keys, block, are inserted into it: “counters” pulses, the decoder, the block of elements OR, the outputs of which are connected to the second inputs of the corresponding keys, the output of the pulse former is connected to the second input of the discharge counter via the second delay element, and to the input reset A direct reading Single venno, wherein the input of frequency divider fed t.aktovyo pulses.

Sources of information taken into account in the examination:

1. USSR Author's Certificate No. 537448, H 04 B 3/46, 1974.