SU761924A1 - Digital frequency meter - Google Patents

Description

The invention relates to a digital measurement technology and can be used to reduce dynamic error in high-speed dynamic systems when it is necessary to convert the pulse repetition rate into a code.

Known digital frequency meters average values of the frequency containing the pulse shaper, connected through a valve with a summing counter, as well as the control unit, including series-connected generator exemplary frequency and frequency divider [1].

A disadvantage of the known devices is low measurement accuracy.

The closest technical solution to the invention is a digital frequency meter containing a pulse shaper, an exemplary frequency generator, a binary frequency multiplier, a delay unit, a summing counter, a code rewriting unit, a reversible counter, and a reverse count trigger [2].

A disadvantage of the known device is low measurement accuracy.

The purpose of the invention is to improve the measurement accuracy.

This goal is achieved by the fact that the device containing the pulse shaper2

owls, serially connected exemplary frequency generator, binary, multiplier, frequencies and delay block, sequentially connected summing counter,

,, 5 code rewriting unit and reversible counter, as well as account reversal trigger, the outputs of which are connected to the second and third inputs of the reversible counter, the fourth input of which is connected to the second output ίο of the binary frequency multiplier, and the second input of the binary frequency multiplier is connected to the first input of the summing the counter and the first output of the first delay block, the second output of which is connected

.15 to the second input of the code rewrite unit, optionally. introduced two blocks of shift of coincident pulses, three elements OR, a trigger with a counting input, two valves, a ZA delay unit, three units of subtraction

20 pulses and three blocks of coincident pulse suppression, the outputs of the first of which are connected to the inputs of the first subtraction unit, the first output of which is connected to the first input of the first valve and the first input of the reverse switch trigger, the second output of the first subtraction unit is connected to the trigger inputs with a counting input , to the first input of the first block of the shift of coincident pulses, to the first input of the second block of suppression of the same name 761924

pulses and through an additional delay unit to the second input of the second block of coincident pulse suppression, the outputs of which are connected to the inputs of the second pulse subtraction unit, the output of the latter is connected to the third input of the binary frequency multiplier, the third output of which is connected to the second input of the first coincident pulse offset unit, the outputs of which through the element OR are connected to the fifth input of the reversible counter, while the third output of the first subtraction unit is connected to the second input of the reverse trigger of the count and to the first input at the second valve, the output of which is connected to the first input of the second element OR, the output of the latter is connected to the second input of the summing counter, the output of the trigger with the counting input is connected to the first input of the third block of suppression of coincident pulses, the outputs of which are connected to the inputs of the third subtraction unit, and the last connected to the second input of the second valve, as well as the trigger output with a counting input connected to the first input of the second shift unit, the outputs of which are connected to the inputs of the third element OR, the output of the last connected to the second input of the first valve, the output of which is connected to the second input of the second element OR, and the output of the pulse shaper is connected to the second input of the third block of suppression of coincident pulses, to the second input of the second block of the shift of coinciding pulses, the first input of the first block of suppression of coinciding pulses and through the second additional delay unit to the second input of the first block of coincident pulse suppression.

The drawing shows a block diagram of the proposed device.

The device contains a pulse shaper 1, a summing counter 2, a reversible counter 3, a trigger 4 for counting reverse, a code rewriting unit 5, an exemplary frequency generator 6, a binary frequency multiplier 7 made of a control counter 8, a counter divider 9 frequency, a block of 10 elements And and a multi-input collecting unit AND OR, delay unit 12, blocks 13, 14, 15 pulse subtraction, blocks 16, 17 and 18 of suppressing coincident pulses, blocks 19 and 20 of shifting coincident pulses, elements 21, 22 and 23 OR, blocks 24 and 25 delay, trigger 26 with counting input, and entili 27 and 28.

The device works as follows.

In the shaper 1 from the input signal

a sequence of pulses of the measured frequency is formed] _x (1). In the block of delay 24 is the delay of the input frequency pulses on the model

ten

15

20

25

thirty

35

40

45

50

55

60

65

time interval The input of block 16 receives two continuous sequences of pulses of the current frequency] _X (T) and shifted) _x (1 — T _o ) for an exemplary time interval. In block 16, the coinciding pulses are suppressed in time, which ensures error-free operation of pulse subtraction unit 13, the output of which produces a continuous sequence of pulses with a repetition rate Δϊχ () = χ (1) -] _X ((–T _O ) equal to the increment measured frequency during the model time interval T _o . At the other outputs of block 13, a signal is generated for the sign of the frequency increment 5Ϊ§ηΧ} _χ (ί). The frequency pulses] _χ (ί) arrive at the counting input of the trigger 26, at the output of which a sequence of pulses is generated halved frequency, i.e. --—

The pulses of this frequency are fed to the first inputs of blocks 17 and 19, the second inputs of which receive pulses of the measured frequency] _χ (ί). In block 17, the coincidence of pulses in time is suppressed, and in block 14, the subtraction of pulses arriving at its inputs. At the output of block 14, a sequence of pulses is formed, the next with the frequency

--— Ρ _χ (ί). In block 19, the coinciding pulses are shifted in time, due to which the collecting element 21 OR is used as a pulse summing unit, at the output of which a sequence of pulses is formed with a repetition frequency] χ (ί) + -P _x (1) ·

Depending on the sign of the increment of the input frequency 5Ϊ§η ^ _χ (· сигна), the signal from the output of block 13 opens either valve 27 or valve 28, from the outputs of one of which through element 23 OR frequency pulses] _x (1) arrive at the counting input summing counter 2, where they are summed over an exemplary time interval T _о , which is formed at the output of frequency counter divider 9 in the binary multiplier 7. Capacity 2 "of frequency counter divider 9 is chosen such that after dividing the input frequency / o from the generator 6, the period following its output impulse would be equal to an exemplary in2 "

time interval T _o = - -. From the weekend to them / 0

pulses of the counter-divider 9 are formed using the block 12 delay control signals, which successively reset the reversible counter 3, then rewrite the code from the summing counter 2 to the reversing counter 3 via block 5, and then reset the summing counter 2 and

control counter 8. Output code

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after the end of the ί'th exemplary time interval of summing counter 2 will be equal to

Kg _x (T4) =

t _p

ΔΛ · (Λ ·)

This code controls the binary multiplier 7 frequency, the output of the collecting element AND OR which produces a sequence of pulses with a frequency

ί-1

ΔΛ7 / 77)

£ 7 (0 _{ T,

Δ /./ Λ)

- the average value of the measured frequency on the g'th exemplary time interval,

- the increment of the current value of the measured frequency during the ϊ-th exemplary interval.

Consequently, in a summation counters ²⁰ ke 2 at the end of each exemplary slot formed code, adjusted for frequency increment value of the input during the exemplary interval, t. E. Reduces the dynamic measurement error. After completion of each exemplary time slot, code Cr _x (T {) of the totaliser 2 is rewritten through the unit 5 in the pre-zeroed ₃₀ down counter 3 to the counting input of which receives impulses frequency Ρ ₂ (ί) from the output member 22. The pulses with frequency P ₂ (P) followings are formed as follows. Pulses with a repetition rate &} _χ (ί) from the output of the block ³⁵ 13 come directly, and to the second input, lingering in the block of delay 25 for the time of the model interval To. In block 18, the pulses coinciding in time are suppressed, and in block 15, it is distinguished by the difference in pulses of the input sequences

i.e., at the output of block 15, an increment of the second order of the measured frequency is allocated during the model time interval. The pulses from the output of the block 15 with the frequency Δ? _Χ (ί) are fed to the counting input of the control counter 8 in the binary frequency multiplier 7. Since the control counter 8 is zeroed at the end of each exemplary time interval, the current value of the control code at the discharge outputs of the control counter 8 in the ί + 1th exemplary time interval will be equal to

The frequency pulses Ρι () from the output of the binary multiplier 7 are fed to one input of block 20, to the other input of which frequency pulses Δ // '/) are received from the output of block 13. V. to block 20 the pulses coinciding in time are shifted. Element 22 OR summarizes the pulses of the input sequences. At the output of element 22 OR is formed by a sequence of pulses with a repetition frequency

. ¹ o

Pulses with repetition rate P ₂ (P) are fed to the counting input of the reversible counter 3, where they are integrated in the ί + 1 st exemplary time interval, and depending on the signal of the increment sign 8. £ ηΔ $ _χ (1) at the output of block 13 which sets the trigger 4, which determines the direction of counting, the current value of the integral is algebraically summed with the number of pulses · Νρ _χ () entered into the reversible counter 3 after the end of the ιth exemplary time interval. The current value of the output code obtained at the outputs of the digits of the reversible counter 3 will be equal to

L (. _S (L ₊ ,) = {

= t,

Δ / _Χ (ί)

cp +

DS + 4; ^άί

+ ^ No. + Ι) r'2T _r ,

δί _χ (Ρί + 0Ί 48Ν _{/ χ} (Τ0

& Ν _{/ Χ} (Τ, _{+ 1} ) \ _{G |} Δ ^ γ / 'Γζ + ΐ). . _(C

where I varies from L · to Λ + ι and

I oi

LH _yr /) =

h

where 1 varies from 7 to Λ ₊ ι. 65

Δ ² ΛΓ _{/ λ} (7 ' _{/ + ι} ) = ΔΑ _{/ χ} (7' _{/ + 1} ) -Δ / ν _ΛΓ (7 ', ·).

The output code of the proposed device by the expression (1) differs from the output code of the prototype by the presence of the fourth

761924

term, different corrective current value of the number of pulses, proportional to the second derivative since the frequency over time, since

= <(() - Δ / Χ - X) // (() · Г _о - - Т _о ) · Т _о = ~ TLLK

g

Due to the correction for the second derivative of the measured frequency in time, it is reduced by the dynamic error when measuring the frequency of a wider class of dynamic signals. The proposed device allows to measure with a smaller dynamic error not only monotonously, but also rapidly changing signals. In addition, the correction is made not according to the value of the rotation of the number of pulses of the measured frequency for the previous exemplary. the time interval, as in the prototype, and the value of the current increments of the first and second order of the measured frequency. This allows you to enter a correction for the current change in the measured frequency, which further reduces the dynamic measurement error. The achieved effect is obtained with virtually no increase in the volume of equipment compared to the prototype.

Claims (1)

Claim A digital frequency meter containing a pulse shaper sequentially connected to an exemplary frequency generator, a binary frequency multiplier and a block for ₇ handles. Successively connected a summing counter, code rewriting unit and reversible counter, a _; also trigger the reverse of the account, the outputs of which are connected to the second and third inputs of the reversible counter, the fourth input of which is connected to the second output of the binary frequency multiplier, and the second input of the binary frequency multiplier is connected to the first input of the summing counter, and the first output of the first delay block, the second the output of which is connected to the second input of the code rewrite unit, which differs from me in that, in order to improve the measurement accuracy, two blocks of coincident pulse shifting are added to it, three elements OR, tr gger with a complementing input, two gates, two delay blocks, three pulses subtracter ¹ and three blocks of suppression of coincident pulses, the outputs of the first of which are connected to the inputs of the first subtraction unit, the first output of which is connected to the first input of the first valve and the first input of the counting reverse switch, the second output of the first subtraction unit connected to the trigger inputs with a counting input, to the first the input of the first block shift matching pulses, the first input of the second block suppression of coincident pulses and through the first additional delay unit to the second input of the second block suppression of coincident pulses, output the latter is connected to the third input of the binary frequency multiplier, the third output of which is connected to the second input of the first coincident pulse shifting unit, the outputs of which through the OR element are connected to the fifth input of the reversing counter, and the third output of the first subtraction unit is connected to the second input of the counting reverse trigger and the first input of the second valve, the output of which is connected to the first input of the second element OR; the output of the latter is connected to the second input of the summing counter, the output of the trigger with the counting input is connected to the first input of the third block of suppression of coincident pulses, the outputs of which are connected to the inputs of the third subtraction unit, and the output of the latter is connected to the second input of the second gate, as well as the output of the trigger with the counting input connected to the first input of the second Shift unit, the outputs of which are connected to the inputs of the third element OR, the output of the latter is connected to the second input of the first valve, the output of which is ^; connected to the second input of the second element OR, and the output of the pulse shaper is connected to the second input of the third block of suppression of coincident pulses, to the second input of the second block of shift of coinciding pulses, the first input of the first block of suppression of coincident pulses, and through the second additional delay block to the second input the first block suppression of coincident pulses.