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SG11201906975PA - Structure for rf use - Google Patents

Structure for rf use

Info

Publication number
SG11201906975PA
SG11201906975PA SG11201906975PA SG11201906975PA SG11201906975PA SG 11201906975P A SG11201906975P A SG 11201906975PA SG 11201906975P A SG11201906975P A SG 11201906975PA SG 11201906975P A SG11201906975P A SG 11201906975PA SG 11201906975P A SG11201906975P A SG 11201906975PA
Authority
SG
Singapore
Prior art keywords
layer
dielectric layer
front surface
support substrate
electrode
Prior art date
Application number
SG11201906975PA
Other languages
English (en)
Inventor
Eric Desbonnets
Bernard Aspar
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201906975PA publication Critical patent/SG11201906975PA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00Antennas with active circuits or circuit elements integrated within them or attached to them
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Waveguides (AREA)
  • Physical Vapour Deposition (AREA)
SG11201906975PA 2017-02-02 2018-01-29 Structure for rf use SG11201906975PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1750870A FR3062517B1 (fr) 2017-02-02 2017-02-02 Structure pour application radiofrequence
PCT/FR2018/050196 WO2018142052A1 (fr) 2017-02-02 2018-01-29 Structure pour application radiofréquence

Publications (1)

Publication Number Publication Date
SG11201906975PA true SG11201906975PA (en) 2019-08-27

Family

ID=58779151

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201906975PA SG11201906975PA (en) 2017-02-02 2018-01-29 Structure for rf use

Country Status (9)

Country Link
US (3) US11043756B2 (fr)
EP (1) EP3577683B1 (fr)
JP (1) JP7098851B2 (fr)
KR (1) KR102520751B1 (fr)
CN (1) CN110235238B (fr)
FR (1) FR3062517B1 (fr)
SG (1) SG11201906975PA (fr)
TW (1) TWI764978B (fr)
WO (1) WO2018142052A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3062517B1 (fr) * 2017-02-02 2019-03-15 Soitec Structure pour application radiofrequence
FR3086096B1 (fr) * 2018-09-14 2021-08-27 Soitec Silicon On Insulator Procede de realisation d'un substrat avance pour une integration hybride
FR3091004B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences
FR3091010B1 (fr) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator Structure de type semi-conducteur pour applications digitales et radiofréquences, et procédé de fabrication d’une telle structure
US11271079B2 (en) * 2020-01-15 2022-03-08 Globalfoundries U.S. Inc. Wafer with crystalline silicon and trap rich polysilicon layer
TWI761255B (zh) 2021-07-08 2022-04-11 環球晶圓股份有限公司 晶圓及晶圓的製造方法
FR3136325A1 (fr) * 2022-06-02 2023-12-08 Soitec Dispositif a ondes elastiques de surface
JP7609154B2 (ja) 2022-11-11 2025-01-07 信越半導体株式会社 高周波デバイス用基板およびその製造方法

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Also Published As

Publication number Publication date
TW201830660A (zh) 2018-08-16
KR102520751B1 (ko) 2023-04-12
US11043756B2 (en) 2021-06-22
EP3577683A1 (fr) 2019-12-11
US20210280990A1 (en) 2021-09-09
FR3062517B1 (fr) 2019-03-15
EP3577683B1 (fr) 2022-09-21
US20190372243A1 (en) 2019-12-05
CN110235238A (zh) 2019-09-13
CN110235238B (zh) 2023-08-29
TWI764978B (zh) 2022-05-21
KR20190112738A (ko) 2019-10-07
US20220368036A1 (en) 2022-11-17
FR3062517A1 (fr) 2018-08-03
US11502428B2 (en) 2022-11-15
WO2018142052A1 (fr) 2018-08-09
JP7098851B2 (ja) 2022-07-12
JP2020509576A (ja) 2020-03-26

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