RU2809209C1 - Logical module - Google Patents

Abstract

FIELD: computer systems.

SUBSTANCE: implementation of any of the simple symmetric Boolean functions depending on n arguments - input binary signals, with n = 7, used in digital computing systems as a means of converting codes.

EFFECT: simplification of the logic module circuit by reducing its price according to Quine. The device contains five majority elements, three XOR elements and an AND element.

1 cl, 1 dwg, 2 tbl

Description

The invention relates to computer technology and can be used to build automation equipment, functional units of control systems, etc.

There are known logical modules (see, for example, RF patent 2709669, class G06F7/57, 2019) that contain exclusive OR elements, majority elements and, using constant settings, implement any of the simple symmetric Boolean functions , , , depending on n arguments - input binary signals, with .

The reason that prevents the achievement of the technical result indicated below when using known logical modules includes limited functionality due to the fact that the implementation of any of the functions is not ensured , , at .

The closest device of the same purpose to the claimed invention in terms of the set of characteristics is the logical module adopted as a prototype (RF patent 2776920, class G06F7/57, 2022), which contains exclusive OR elements, majority elements and, using a constant setting, implements any of simple symmetric Boolean functions , , , depending on n arguments - input binary signals, with .

The reason that prevents the achievement of the technical result indicated below when using the prototype is the circuit complexity, due to the fact that the Quine price of the prototype circuit is 27.

The technical result of the invention is to simplify the logic module circuit by reducing its cost according to Quine while maintaining the functionality of the prototype.

The specified technical result when implementing the invention is achieved by the fact that in a logical module containing three exclusive OR elements and five majority elements, the i -th ( ) input j -th ( ) of the exclusive OR element and the first, third inputs of the third majority element are connected, respectively, to the i -th input of the j -th majority element and the outputs of the first, second exclusive OR elements, the output of the first and third input of the fourth majority elements are connected, respectively, to the second input of the third exclusive OR element and the output of the second majority element, and the second input of the third, i -th input of the j -th and first input of the fifth majority elements are connected respectively to the fourth, ( )-th information and second setting inputs of the logical module, the first setting input of which is connected to the first input of the third exclusive OR element, the peculiarity is that the AND element, the first, second inputs of the third exclusive OR element and the first, second inputs of the fourth The majority element is connected, respectively, to the first, second inputs of the AND element and the outputs of the third exclusive OR element, the majority element, and the output of the AND element, the third input and the output of the fifth majority element are connected, respectively, to the second input of the fifth, the output of the fourth majority elements and the output of the logical module.

The drawing shows a diagram of the proposed logical module.

The logical module contains majority elements 1 ₁ ,…,1 ₅ , elements exclusive or 2 ₁ , 2 ₂ , 2 ₃ and element AND 3, with the i -th ( ) input element 1 _j ( ) and the first, second inputs of element 3 are connected, respectively, to the i -th input of element 2 _j and the first, second inputs of element 2 ₃ , second input of element 3, first, third inputs of element 1 ₃ , second, third inputs of element 1 ₅ and first, the second, third inputs of element 1 ₄ are connected respectively to the outputs of elements 1 ₁ , 2 ₁ , 2 ₂ , 3, 1 ₄ and 2 ₃ , 1 ₃ , 1 ₂ , and the second input of element 1 ₃ , i - th input of element 1 _j and the first input of element 3 is connected respectively to the fourth, ( )-th information and first setting inputs of the logical module, the second setting input and output of which are connected, respectively, to the first input and output of element 1 ₅ .

The operation of the proposed logical module is carried out as follows. Binary signals are supplied to its first, ..., seventh information and first, second tuning inputs, respectively and signals constant settings. Table 1 and Table 2 below show the values of internal signals, respectively. ( ), of the proposed logical module, obtained for all possible sets of signal values , and the values of its output signal Z , obtained for all possible sets of signal values at 1) ; 2) , ; 3) , .

Table 1 000 00 100 01 001 01 101 10 010 01 110 10 011 10 111 eleven table 2 1) 2) 3) 1) 2) 3) Z Z Z Z Z Z 0 00 00 0 0 0 1 00 00 0 0 0 0 00 01 0 0 0 1 00 01 1 0 0 0 00 10 1 0 0 1 00 10 1 0 0 0 00 eleven 1 0 0 1 00 eleven 1 1 0 0 01 00 0 0 0 1 01 00 1 0 0 0 01 01 1 0 0 1 01 01 1 0 0 0 01 10 1 0 0 1 01 10 1 1 0 0 01 eleven 1 1 0 1 01 eleven 1 1 0 0 10 00 1 0 0 1 10 00 1 0 0 0 10 01 1 0 0 1 10 01 1 1 0 0 10 10 1 1 0 1 10 10 1 1 0 0 10 eleven 1 1 0 1 10 eleven 1 1 1 0 eleven 00 1 0 0 1 eleven 00 1 1 0 0 eleven 01 1 1 0 1 eleven 01 1 1 0 0 eleven 10 1 1 0 1 eleven 10 1 1 1 0 eleven eleven 1 1 1 1 eleven eleven 1 1 1

If or , or , , then according to table. 1, table. 2 we have

or or ,

Where there are simple symmetric Boolean functions of seven arguments (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M.: Energia, 1974).

The above information allows us to conclude that the proposed logical module, using a constant setting, implements any of the simple symmetric Boolean functions , , , depending on n arguments - input binary signals, with . At the same time, the circuit of the proposed logical module is simpler than that of the prototype, since its price according to Quine is 25.

Claims (1)

A logical module designed to implement simple symmetric Boolean functions, containing three exclusive OR elements and five majority elements, with the i -th ( ) input j -th ( ) of the exclusive OR element and the first, third inputs of the third majority element are connected, respectively, to the i -th input of the j -th majority element and the outputs of the first, second exclusive OR elements, the output of the first and third input of the fourth majority elements are connected, respectively, to the second input of the third exclusive OR element and the output of the second majority element, and the second input of the third, i -th input of the j -th and first input of the fifth majority elements are connected respectively to the fourth, ( )-th information and second setting inputs of the logical module, the first setting input of which is connected to the first input of the third exclusive OR element, characterized in that an AND element is introduced into it, the first, second inputs of the third exclusive OR element and the first, second inputs of the fourth majority element are connected, respectively, to the first, second inputs of the AND element and the outputs of the third exclusive OR element, the majority element, and the output of the AND element, the third input and the output of the fifth majority element are connected, respectively, to the second input of the fifth, the output of the fourth majority elements and the output of the logical module.