RU2803625C1 - Logic converter - Google Patents

Abstract

FIELD: computer systems.

SUBSTANCE: logic converter is designed to implement any of the simple symmetrical Boolean functions τ₁, τ₂, τ₆, τ₇, depending on seven arguments - input binary signals, and can be used in digital computer systems as a means of converting codes. The logic converter contains eight majority elements (1₁,…, 1₈) and two EXCLUSIVE OR elements (2₁, 2₂).

EFFECT: simplification of the logic converter circuit is achieved by reducing its Quine price while maintaining the functionality of the prototype.

1 cl, 1 dwg, 2 tbl

Description

The invention relates to computer technology and can be used to build automation equipment, functional units of control systems, etc.

There are known logical converters (see, for example, RF patent 2689815, class G06F7/57, 2019) that contain majority elements and, using constant tuning, implement any of the simple symmetric Boolean functions , depending on seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using known logic converters is the circuit complexity due to the fact that the Quine price of the circuit, in particular, the mentioned analogue, is 36.

The closest device of the same purpose to the claimed invention in terms of the set of features is a logic converter adopted as a prototype (RF patent 2762620, class G06F7/57, 2021), which contains majority elements and, using a constant setting, implements any of the simple symmetric Boolean functions , depending on seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using the prototype is the circuit complexity, due to the fact that the Quine price of the prototype circuit is 33.

The technical result of the invention is to simplify the logic converter circuit by reducing its Quine price while maintaining the functionality of the prototype.

The specified technical result when implementing the invention is achieved by the fact that in a logic converter containing eight majority elements, the outputs of the third, fourth, third input of the eighth and the first inputs of the third, sixth majority elements are connected, respectively, to the second inputs of the fourth, fifth, the output of the second majority elements and the first , the second tuning inputs of the logical converter, the peculiarity is that two exclusive OR elements are additionally introduced into it, the third inputs of the fourth, fifth majority elements, i -th ( ) input and output of the j -th ( ) of the exclusive OR element are connected respectively to the outputs of the eighth, seventh, i -th input of the j -th and second input ( )-th majority elements, the third inputs of the third, sixth and second inputs of the seventh, eighth majority elements are connected, respectively, to the outputs of the second, first exclusive OR elements and the outputs of the sixth, first majority elements, and the first, second, third inputs of the j -th element are exclusive OR , the third input of the seventh and output of the fifth majority elements are connected respectively to ( )th, ( )th, ( )-th, seventh information inputs and the output of the logic converter, the second and first tuning inputs of which are connected, respectively, to the first inputs of the fourth, fifth, eighth and the first input of the seventh majority elements.

The drawing shows a diagram of the proposed logic converter.

The logic converter contains majority elements 1 ₁ ,…, 1 ₈ and exclusive OR elements 2 ₁ , 2 ₂ , and the outputs of elements 1 ₁ , 2 ₁ , 2 ₂ , 1 ₃ , 1 ₄ , 1 ₆ and the third inputs of elements 1 ₃ , 1 ₄ , 1 ₅ , 1 ₆ , 1 ₈ are connected respectively to the second inputs of elements 1 ₈ , 1 ₃ , 1 ₆ , 1 4, 1 ₅ , 1 ₇ and the outputs of elements 2 ₂ , 1 ₈ , _{1 7 ,} 2 ₁ , 1 ₂ , i -th ( ) input element 1 _j ( ) is connected to the i -th input of element 2 _j , and the first, second, third inputs of element 2 _j , the third input of element 1 ₇ and the output of element 1 ₅ are respectively ( )th, ( )th, ( )-th, seventh information inputs and output of the logical converter, the first and second adjustment inputs of which are connected, respectively, to the first inputs of elements 1 ₃ , 1 ₇ and the first inputs of elements 1 ₄ , 1 ₅ , 1 ₆ , 1 ₈ .

The operation of the proposed logic converter is carried out as follows. At its first and second tuning inputs, the necessary signals are fixed accordingly constant settings. Binary signals are supplied to its first,..., seventh information inputs, respectively . Table 1 below shows the values of internal signals ( ), of the proposed logic converter, obtained for all possible sets of signal values . Table 2 below shows the values of its output signal Z obtained for all possible sets of signal values at 1) ; 2) , ; 3) , ; 4) .

Table 1 000 00 100 01 001 01 101 10 010 01 110 10 011 10 111 eleven

table 2 1) 2) 3) 4) 1) 2) 3) 4) Z Z Z Z Z Z Z Z 0 00 00 0 0 0 0 1 00 00 1 0 0 0 0 00 01 1 0 0 0 1 00 01 1 1 0 0 0 00 10 1 1 0 0 1 00 10 1 1 0 0 0 00 eleven 1 1 0 0 1 00 eleven 1 1 0 0 0 01 00 1 0 0 0 1 01 00 1 1 0 0 0 01 01 1 1 0 0 1 01 01 1 1 0 0 0 01 10 1 1 0 0 1 01 10 1 1 0 0 0 01 eleven 1 1 0 0 1 01 eleven 1 1 0 0 0 10 00 1 1 0 0 1 10 00 1 1 0 0 0 10 01 1 1 0 0 1 10 01 1 1 0 0 0 10 10 1 1 0 0 1 10 10 1 1 0 0 0 10 eleven 1 1 0 0 1 10 eleven 1 1 1 0 0 eleven 00 1 1 0 0 1 eleven 00 1 1 0 0 0 eleven 01 1 1 0 0 1 eleven 01 1 1 0 0 0 eleven 10 1 1 0 0 1 eleven 10 1 1 1 0 0 eleven eleven 1 1 1 0 1 eleven eleven 1 1 1 1

If or , or , or , then according to table. 1, table. 2 accordingly we have

or or

or ,

Where there are simple symmetric Boolean functions of seven arguments (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M.: Energia, 1974).

The above information allows us to conclude that the proposed logic converter, using a constant setting, implements any of the simple symmetric Boolean functions , depending on seven arguments - input binary signals, while the circuit of the proposed logic converter is simpler than that of the prototype, since its price according to Quine is 30.

Claims (1)

A logic converter designed to implement simple symmetric Boolean functions, containing eight majority elements, wherein the outputs of the third, fourth, third input of the eighth and first inputs of the third, sixth majority elements are connected, respectively, to the second inputs of the fourth, fifth, the output of the second majority elements and the first, second tuning inputs of the logical converter, characterized in that it additionally contains two exclusive OR elements, the third inputs of the fourth and fifth majority elements, the i -th ( $$i=\overline{1.3}$$ ) input and output of the j -th ( $$j=\overline{1.2}$$ ) of the exclusive OR element are connected respectively to the outputs of the eighth, seventh, i -th input of the j -th and second input ( $$3\times j$$ )-th majority elements, the third inputs of the third, sixth and second inputs of the seventh, eighth majority elements are connected, respectively, to the outputs of the second, first exclusive OR elements and the outputs of the sixth, first majority elements, and the first, second, third inputs of the j -th element are exclusive OR , the third input of the seventh and output of the fifth majority elements are connected respectively to ( $$3\times j-2$$ )-m, ( $$3\times j-1$$ )-m, ( $$3\times j$$ )-th, seventh information inputs and the output of the logical converter, the second and first tuning inputs of which are connected, respectively, to the first inputs of the fourth, fifth, eighth and the first input of the seventh majority elements.